An extensible, system-on-programmable-chip, content-aware internet firewall

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 2778, Issue , 2003, Pages 859-868

  Lockwood, John W ^a   Neely, Christopher ^a   Zuver, Christopher ^a   Moscola, James ^a   Dharmapurikar, Sarang ^a   Lim, David ^a  

^a WASHINGTON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER CRIME; COMPUTER HARDWARE; COMPUTER SYSTEM FIREWALLS; DENIAL-OF-SERVICE ATTACK; HARDWARE; INTERNET; INTERNET PROTOCOLS; PACKET NETWORKS; RECONFIGURABLE HARDWARE; TERNARY CONTENT ADRESSABLE MEMORY;

HARDWARE MODULES; INTERNET FIREWALLS; NETWORK INTRUSIONS; PACKET PROCESSING; REGULAR-EXPRESSION MATCHING; RUN TIME RECONFIGURATION; SYSTEM ON PROGRAMMABLE CHIPS; TERNARY CONTENT ADDRESSABLE MEMORY;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 35248880225     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-45234-8_83     Document Type: Article

References (17)

1. R. Franklin, D. Carver, and B. L. Hutchings, "Assisting network intrusion detection with reconfigurable hardware," in FCCM, (Napa, CA), Apr. 2002.
2. J. W. Lockwood, "Evolvable internet hardware platforms," in The Third NASA/DoD Workshop on Evolvable Hardware (EH'2001), pp. 271-279, July 2001.
3. F. Braun, J. Lockwood, and M. Waldvogel, "Reconfigurable router modules using network protocol wrappers," in Field-Programmable Logic and Applications (FPL), (Belfast, Northern Ireland), pp. 254-263, Aug. 2001.
4. Y. Cho, S. Nahab, and W. H. Mangione-Smith, "Specialized hardware for deep network packet filtering," in Field Programmable Logic and Applications (FPL), (Montpellier, France), Sept. 2002.
5. J. Moscola, J. Lockwood, R. P. Loui, and M. Pachos, "Implementation of a content-scanning module for an Internet firewall," in FCCM, (Napa, CA), Apr. 2003.
6. J.-L. Brelet, "Using block RAM for high performance read/write CAMs." Xilinx XAPP204, May 2002.
7. H. Duan, J. W. Lockwood, S. M. Kang, and J. Will, "High-performance OC-12/OC-48 queue design prototype for input-buffered ATM switches," in INFOCOM'97, (Kobe, Japan), pp. 20-28, Apr. 1997.
8. S. Dharmapurikar and J. Lockwood, "Synthesizable design of a multi-module memory controller." Washington University, Department of Computer Science, Technical Report WUCS-01-26, Oct. 2001.
9. "Acceleration of Algorithms in Hardware." http://www.arl.wustl.edu/ ∼lockwood/class/cs535/, Sept. 2001.
10. "Reconfigurable System-On-Chip Design." http://www.arl.vustl.edu/ ∼lockwood/class/cs536/, Dec. 2002.
11. D. Lim, C. E. Neely, C. K. Zuver, and J. W. Lockwood, "Internet-based tool for system-on-chip integration," in International Conference on Microelectronic Systems Education (MSE), (Anaheim, CA), June 2003.
12. C. E. Neely, C. K. Zuver, and J. W. Lockwood, "Internet-based tool for system-on-chip project testing and grading," in International Conference on Microelectronic Systems Education (MSE), (Anaheim, CA), June 2003.
13. E. L. Horta, J. W. Lockwood, D. E. Taylor, and D. Parlour, "Dynamic hardware plugins in an FPGA with partial run-time reconfiguration," in Design Automation Conference (DAC), (New Orleans, LA), June 2002.
14. T. Sproull, J. W. Lockwood, and D. E. Taylor, "Control and configuration software for a reconfigurable networking hardware platform," in IEEE Symposium on Field-Programmable Custom Computing Machines, (FCCM), (Napa, CA), Apr. 2002.
15. S. McMillan and S. Guccione, "Partial run-time reconfiguration using JRTR," in Field-Programmable Logic and Applications (FPL), (Villach, Austria), pp. 352-360, Aug. 2000.
16. H. Fallside and M. J. S. Smith, "Internet connected FPL," in Field-Programmable Logic and Applications (FPL), (Villach, Austria), pp. 48-57, Aug. 2000.
17. J. W. Lockwood, J. S. Turner, and D. E. Taylor, "Field programmable port extender (FPX) for distributed routing and queuing," in ACM International Symposium on Field Programmable Gate Arrays (FPGA'2000), (Monterey, CA, USA), pp. 137-144, Feb. 2000.