Extending concurrency of transactional memory programs by using value prediction

Proceedings of the 6th ACM Conference on Computing Frontiers, CF 2009

Volumn , Issue , 2009, Pages 11-20

  Pant, Salil ^a   Byrd, Gregory T ^a  

^a NORTH CAROLINA STATE UNIVERSITY   (United States)

Author keywords

Design; Performance

Indexed keywords

CRITICAL SECTIONS; DESIGN AND IMPLEMENTATIONS; IMPROVE PERFORMANCE; LOCK-BASED SYNCHRONIZATION; MEMORY CONTROLLER; PERFORMANCE; SPECULATIVE SYNCHRONIZATIONS; TRANSACTIONAL MEMORY;

BENCHMARKING; DESIGN; PARALLEL ARCHITECTURES; STORAGE ALLOCATION (COMPUTER);

CONCURRENCY CONTROL;

EID: 84885764504     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1531743.1531748     Document Type: Conference Paper

References (20)

1. SPECjbb2000. http://www.spec.org/jbb200.
2. C. S. Ananian et al. Unbounded transactional memory. IEEE Micro, 26(1):59-69, 2006.
3. J. Bobba et al. Performance pathologies in hardware transactional memory. IEEE Micro, 28(1):32-41, Jan-Feb 2008.
4. M. Cintra and J. Torrellas. Eliminating squashes through learning cross-thread violations in speculative parallelization for multiprocessors. In Intl. Symp.on High-Perf. Comput. Archit., pages 43-54, 2002.
5. L. Hammond et al. Transactional coherence and consistency: Simplifying parallel hardware and software. IEEE Micro, 24(6):92-103, 2004.
6. M. Herlihy et al. Software transactional memory for dynamic-sized data structures. In Symp. on Principles of Dist. Comput., pages 92-101, 2003.
7. M. Herlihy and J. E. B. Moss. Transactional memory: Architectural support for lock-free data structures. In Intl. Symp. on Comput. Archit., pages 289-300, 1993.
8. A. Kägi, D. Burger, and J.R. Goodman. Efficient synchronization: Let them eat QOLB. Intl. Symp. on Computer Architecture (ISCA), pages 170-180, June 1997.
9. S. Kumar et al. Hybrid transactional memory. In Symp. on Princ. and Practice of Parallel Programming, pages 209-220, 2006.
10. P. S. Magnusson et al. Simics: A full system simulation platform. Computer, 35(2):50-58, 2002.
11. M. M. K. Martin, D. J. Sorin, et al. Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset. SIGARCH Comput. Archit. News, 33(4):92-99, 2005.
12. J. M. Mellor-Crummey and M. L. Scott. Algorithms for scalable synchronization on shared-memory multiprocessors. ACM Trans. Comput. Syst., 9(1):21-65, 1991.
13. C. C. Minh et al. STAMP: Stanford transactional applications for multi-processing. In IEEE Intl. Symp. on Workload Characterization, pages 35-46, 2008.
14. K.E. Moore, J. Bobba, et al. LogTM: log-based transactional memory. In Intl. Symp. on High-Perf. Comput. Archit., pages 254-265, 2006.
15. R. Rajwar and J. R. Goodman. Transactional lock-free execution of lock-based programs. SIGPLAN Not., 37(10):5-17, 2002.
16. R. Rajwar, M. Herlihy, and K. Lai. Virtualizing transactional memory. In Intl. Symp. on Comput. Archit., pages 494-505, 2005.
17. H. E. Ramadan, C. J. Rossbach, O. S. Hofmann, and E. Witchel. Dependence-aware transactions for increased concurrency. In Intl. Symp. on Microarchitecture, pages 246-257, 2008.
18. J. G. Steffan et al. Improving value communication for thread-level speculation. In Intl. Symp. on High-Perf. Comput. Archit., pages 65-72, 2002.
19. Sun Microsystems. UltraSPARC III Cu User's manual, 2004. Version 2.2.1.
20. S. Woo et al. Methodological considerations and characterization of the SPLASH-2 parallel application suite. In Intl. Symp. on Comput. Archit., 1995.