Cache coherence enabled adaptive refresh for volatile STT-RAM

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2013, Pages 1247-1250

  Li, Jianhua ^a,b   Shi, Liang ^a,b   Li, Qing'an ^a,c   Xue, Chun Jason ^a   Chen, Yiran ^d   Xu, Yinlong ^b  

^a CITY UNIVERSITY OF HONG KONG   (Hong Kong)

^b UNIVERSITY OF SCIENCE AND TECHNOLOGY OF CHINA   (China)

^c WUHAN UNIVERSITY   (China)

^d University of Pittsburgh   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MEMORY; TUNNEL JUNCTIONS;

CACHE COHERENCE; CACHE COHERENCE PROTOCOLS; CACHE PERFORMANCE; FULL-SYSTEM SIMULATION; MAGNETIC TUNNEL JUNCTION; READ/WRITE OPERATIONS; RETENTION TIME; SPIN TRANSFER TORQUE;

MAGNETIC DEVICES;

EID: 84885621749     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.7873/date.2013.258     Document Type: Conference Paper

References (15)

1. C. Bienia. Benchmarking Modern Multiprocessors. PhD thesis, Princeton University, January 2011.
2. E. Chen, D. Apalkov, et al. Advances and Future Prospects of Spin-Transfer Torque Random Access Memory. IEEE Transactions on Magnetics, 46(6):1873-1878, 2010.
3. M. Hosomi, H. Yamagishi, et al. A Novel Nonvolatile Memory with Spin Torque Transfer Magnetization Switching: Spin-RAM. In International Electron Devices Meeting (IEDM '05), pages 459-462, 2005.
4. J. Hu, C. J. Xue, et al. Reducing Write Activities on Non-Volatile Memories in Embedded CMPs via Data Mgration and Recomputation. In Annual Design Automation Conference (DAC '10), pages 350-355, 2010.
5. A. Jog, A. K. Mishra, et al. Cache Revive: Architecting Volatile STT-RAM Caches for Enhanced Performance in CMPs. In Annual Design Automation Conference (DAC '12), pages 243-252, 2012.
6. A. Kahng, B. Li, et al. Orion 2.0: A Fast and Accurate NoC Power and Area Model for Early-Stage Design Space Exploration. In Design, Automation Test in Europe (DATE '09), pages 423-428, 2009.
7. J. Li, C. Xue, and Y. Xu. STT-RAM based Energy-Efficiency Hybrid Cache for CMPs. In International Conference on Very Large Scale Integration (VLSI-SoC '11), pages 31-36, 2011.
8. P. Magnusson, M. Christensson, et al. Simics: A Full System Simulation Platform. Computer, 35(2):50-58, feb 2002.
9. M. M. K. Martin, D. J. Sorin, et al. Alameldeen, K. E. Moore, M. D. Hill, and D. A. Wood. Multifacet's General Execution-Driven Multiprocessor Simulator (GEMS) toolset. SIGARCH Computer Architecture News, 33:92-99, 2005.
10. C. Smullen, V Mohan, et al. Relaxing Non-Volatility for Fast and Energy-Efficient STT-RAM Caches. In International Symposium on High Performance Computer Architecture (HPCA '11), pages 50-61, 2011.
11. D. J. Sorin, M. D. Hill, and D. A. Wood. A Primer on Memory Consistency and Cache Coherence. Synthesis Lectures on Computer Architecture. Morgan and Claypool Publishers, May 2011.
12. J. Li, L. Shi, C. Xue, C. Yang and Y Xu. Exploiting Set-Level Write Non-Uniformity for Energy-Efficient NVM-based Hybrid Cache. In IEEE Symposium on Embedded Systems for Real-Time Multimedia (ESTIMedia '11), pages 19-28, 2011.
13. Z. Sun, X. Bi, et al. Multi Retention Level STT-RAM Cache Designs with A Dynamic Refresh Scheme. In IEEE/ACM International Symposium on Microarchitecture (MICRO '11), pages 329-338, 2011.
14. M. B. Taylor, J. Kim, et al. The RAW Microprocessor: A Computational Fabric for Software Circuits and General-Purpose Programs. IEEE Micro, 22(2):25-35, Mar. 2002.
15. C. J. Xue, Y Zhang, et al. Emerging Non-Volatile Memories: Opportunities and Challenges. In International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '11), pages 325-334, 2011.