Multi retention level STT-RAM cache designs with a dynamic refresh scheme

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue , 2011, Pages 329-338

  Sun, Zhenyu ^a   Bi, Xiuyuan ^a   Li, Hai ^a   Wong, Weng Fai ^b   Ong, Zhong Liang ^b   Zhu, Xiaochun ^c   Wu, Wenqing ^c  

^a POLYTECHNIC UNIVERSITY   (United States)

^b NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

^c QUALCOMM INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

3 LEVELS; CACHE CAPACITY; CACHE DESIGN; CACHE HIERARCHIES; CACHE MISS; CONTROLLED DYNAMICS; DATA MIGRATION; DATA RETENTION TIME; DATA VALIDITY; LEAKAGE POWER; MAGNETIC TUNNELING JUNCTIONS; NONVOLATILITY; ON-CHIP CACHE; PERFORMANCE IMPROVEMENTS; RADIATION HARDNESS; RANDOM ACCESS MEMORIES; REDUCED DATA; RETENTION CHARACTERISTICS; RETENTION LEVELS; SPIN TRANSFER TORQUE; STANDBY POWER; TECHNOLOGY SCALING; TOTAL ENERGY; WRITE OPERATIONS;

CACHE MEMORY; MAGNETIC DEVICES; STATIC RANDOM ACCESS STORAGE;

DESIGN;

EID: 84863355068     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2155620.2155659     Document Type: Conference Paper

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