Circuit performance oriented device optimization using BSIM3 pre-silicon model parameters

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2000, Pages 371-374

  Miyama, Mikako ^a   Kamohara, Shiro ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT PERFORMANCE; CRITICAL PATHS; DEVICE OPTIMIZATION; DEVICE PERFORMANCE; GENERATION METHOD; INITIAL DESIGN; MODEL PARAMETERS; OPTIMIZATION METHODOLOGY;

COMPUTER AIDED DESIGN; ELECTRIC NETWORK ANALYSIS; SILICON;

OPTIMIZATION;

EID: 84884679490     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/368434.368684     Document Type: Conference Paper

References (5)

1. B.Davari, "CMOS Technology Scaling, 0.1mm and Beyond,"pp.555- 558, IEDM96.
2. C. Hu, "Gate Oxide Scaling Limits and Projection," pp.319-322, IEDM96.
3. K. Chen, H. C. Wann, P. K. Ko, C. Hu, "The Impact of Device Scaling and Power Supply Change on CMOS Gate Performance,"IEEE Electron Device Letter, Vol.17, no. 5, pp.1-3, MAY 1996.
4. M. Miyama, S. Kamohara, M. Hiraki, K. Onozawa, H. Kunitomo, "Pre-Silicon Parameter Generation Methodology using BSIM3 for Device/Circuit Concurrent Design,"pp.359-362, CICC99.
5. Y.Cheng, M. Chan, K. Hui, M. Jeng, Z, P. Ko. C. Hu, et al., "BSIM3v3 Manual," 1996.