Low power analog design in scaled technologies

Proceedings of the Topical Workshop on Electronics for Particle Physics, TWEPP 2009

Volumn , Issue , 2009, Pages 103-109

  Baschirotto, A ^a,b   Chironi, V ^b   Cocciolo, G ^b   D'Amico, S ^b   De Matteis, M ^b   Delizia, P ^b  

^a UNIVERSITY OF MILANO BICOCCA   (Italy)

^b UNIVERSITY OF SALENTO   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG IC DESIGN; CHIP AREAS; DIGITAL PARTS; GATE OXIDE; POWER LEAKAGE; SCALED CMOS; SCALED TECHNOLOGIES; SUPPLY VOLTAGES;

CMOS INTEGRATED CIRCUITS;

DESIGN;

EID: 84884177927     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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