An extra low-power 1Tbit/s bandwidth PLL/DLL-less eDRAM PHY using 0.3V low-swing IO for 2.5D CoWoS application

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2013, Pages

  Lin, Mu Shan ^a   Tsai, Chien Chun ^a   Chang, Chih Hsien ^a   Huang, Wen Hung ^a   Hsu, Ying Yu ^a   Yang, Shu Chun ^a   Fu, Chin Ming ^a   Chou, Mao Hsuan ^a   Huang, Tien Chien ^a   Chen, Ching Fang ^a   Huang, Tze Chiang ^a   Adham, Saman ^a   Wang, Min Jer ^a   Shen, William Wu ^a   Mehta, Ashok ^a  

^a TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

40NM CMOS; 65-NM TECHNOLOGIES; DATA SAMPLING; GOOD TIMING; POWER EFFICIENCY; SILICON INTERPOSERS; SMALL AREA; TIMING COMPENSATIONS;

CMOS INTEGRATED CIRCUITS; PROGRAMMABLE LOGIC CONTROLLERS; VLSI CIRCUITS;

BANDWIDTH;

EID: 84883802762     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. B. Kim et al, "A 10-Gb/s Compact Low-Power Serial I/O With DFE-IIR Equalization in 65-nm," JSSC, 2009
2. J. Kim et al, "A 1.2V 12.8GB/s 2Gb Mobile Wide-I/O DRAM with 4x128 I/Os Using TSV-Based Stacking," ISSCC, 2011
3. J. Kim et al, "1-Tbyte/s 1-Gbit DRAM Architecture Using 3-D Interconnect for High-Throughput Computing," JSSC, 2011
4. Y. Liu et al, "A Compact Low-Power 3D I/O in 45nm CMOS," ISSCC, 2012