A hybrid CBRAM/CMOS Look-Up-Table structure for improving performance efficiency of Field-Programmable-Gate-Array

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2013, Pages 2440-2443

  Onkaraiah, Santhosh ^a   Turkyilmaz, Ogun ^a   Reyboz, Marina ^a   Clermidy, Fabien ^a   Vianello, Elisa ^a   Portal, Jean Michel ^b   Muller, Christophe ^b  

^a CEA LETI   (France)

^b AIX MARSEILLE UNIVERSITY   (France)

Author keywords

CBRAM; compact model; LUT; NV FPGA; NV RAM; resistive memory

Indexed keywords

CBRAM; COMPACT MODEL; LUT; NV-FPGA; NV-RAM; RESISTIVE MEMORY;

COMPUTER ARCHITECTURE; STATIC RANDOM ACCESS STORAGE;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 84883429248     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2013.6572372     Document Type: Conference Paper

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