Reliability-Aware Synthesis of Combinational Logic with Minimal Performance Penalty

IEEE Transactions on Nuclear Science

Volumn 60, Issue 4, 2013, Pages 2776-2781

  Limbrick, Daniel B ^a   Mahatme, Nihaar N ^b   Robinson, William H ^b   Bhuva, Bharat L ^b  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b VANDERBILT UNIVERSITY   (United States)

Author keywords

Combinational logic; pulse width; reliability aware synthesis; single event transient; soft error

Indexed keywords

COMBINATIONAL LOGIC; PULSEWIDTHS; RELIABILITY-AWARE SYNTHESIS; SINGLE EVENT TRANSIENTS; SOFT ERROR;

ERROR CORRECTION; MICROPROCESSOR CHIPS;

RELIABILITY;

EID: 84882811879     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2013.2240699     Document Type: Article

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