Design space exploration and optimization of path oblivious RAM in secure processors

Proceedings - International Symposium on Computer Architecture

Volumn , Issue , 2013, Pages 571-582

  Ren, Ling ^a   Yu, Xiangyao ^a   Fletcher, Christopher W ^a   Van Dijk, Marten ^a   Devadas, Srinivas ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BASELINE CONFIGURATIONS; COMPUTATION MODEL; DESIGN SPACE EXPLORATION; INTEGRITY VERIFICATIONS; PERFORMANCE-DRIVEN; SECURE PROCESSORS; SECURITY COMMUNITY; TAMPER-RESISTANT;

COMPUTER ARCHITECTURE; COMPUTER SYSTEMS; DATA PRIVACY; OPTIMIZATION;

RANDOM ACCESS STORAGE;

EID: 84881169695     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2485922.2485971     Document Type: Conference Paper

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