IVEC: Off-chip memory integrity protection for both security and reliability

Proceedings - International Symposium on Computer Architecture

Volumn , Issue , 2010, Pages 395-406

  Huang, Ruirui ^a   Edward Suh, G ^a  

^a Cornell University ^*  (United States)

Author keywords

Error correction; Error detection; Fault tolerance; Memory systems; Reliability; Security

Indexed keywords

BANDWIDTH OVERHEADS; CACHE BLOCKS; DRAM CHIPS; ECC SCHEME; ERROR CORRECTING CODE; ERROR CORRECTION CAPABILITY; EXPERIMENTAL STUDIES; INTEGRITY PROTECTION; MALICIOUS ATTACK; MEMORY SYSTEMS; MULTI-BIT ERROR; OFF-CHIP MEMORIES; PARITY BITS; PHYSICAL ATTACKS; SINGLE-BIT; VERIFICATION TECHNIQUES;

COMPUTER ARCHITECTURE; COMPUTERS; DYNAMIC RANDOM ACCESS STORAGE; ERROR CORRECTION; ERROR DETECTION; FAULT DETECTION; FAULT TOLERANCE; FAULT TOLERANT COMPUTER SYSTEMS; NETWORK SECURITY; QUALITY ASSURANCE;

RANDOM ERRORS;

EID: 77954980229     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1815961.1816015     Document Type: Conference Paper

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