A CAD framework for generating self-checking multipliers based on residue codes

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 1999, Pages 122-129

  Noufal, I A ^a   Nicolaidis, M ^a  

^a TIMA LABORATORY   (France)

Author keywords

Fault Secure Circuits; Multipliers; Residue Arithmetic Codes; Self Checking Circuits

Indexed keywords

AUTOMATIC GENERATION; COMPATIBLE SCHEMES; FAULT SECURE; HARDWARE OVERHEADS; LOW HARDWARE COSTS; RESIDUE ARITHMETIC; SELF CHECKING CIRCUITS; SELF-CHECKING MULTIPLIER;

COSTS; DESIGN; EXHIBITIONS; FORECASTING; FREQUENCY MULTIPLYING CIRCUITS; TOOLS;

HARDWARE;

EID: 84881145671     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.1999.761107     Document Type: Conference Paper

References (24)

1. [AND71] D. A. ANDERSON, "Design of self checking digital networks using coding techniques". Urbana, CSL/University of IIIionis, Sept. 1971 (report n. 527).
2. [AVI73] A. Avizienis, "Arithmetic Algorithms for Error-Coded Operands" IEEE Trans. on Comput., Vol. C-22, No. 6, pp.567-572, June 1973.
3. [BRE82] R. P. Brent, H. T. Kung, A Regular Layout for Parallel Adders", IEEE Transactions On Computers, Vol. C31, pp 261-264, March 1982.
4. [BOE97] E. Boehl, Th. Lindenkreuz, R. Stephan, "The Fail-Stop Controller AE11", ITC pp.567-577, Nov. 1997.
5. [DUA97] R.O. Duarte, M. Nicolaidis, H. Bederr, Y. Zorian, "Efficient Fault-Secure Shifter Design", European Design & Test Conference, Paris, March 1997.
6. [DUF96] Jen-Louis Dufour, "Safety Computations in Integrated circuits", VTS. pp. 169-172, April 28-May 1, 1996.
7. [GAR68] O.N. Garcia, T.R.N. Rao T, "On the method of checking logical operations", Proc. 2nd Annual Princeton Conf. Inform. Sci. Sys., pp. 89-95 (1968).
8. [HAN87] T. Han, D. A. Carlson, "Fast Area-Efficient VLSI Adders", Proc of 8th Symposium on Computer Arithmetic, pp. 49-56, May 1987.
9. [HWA79] K. Hwang, Computer Arithmetic, Principles, Architecture and Design, John Wiley and Sons, New York, 1979.
10. [KOG73] P. M. Kogge and H. S. Stone, A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations, IEEE Transactions on Computers, Vol. C-22, No.8, pp. 786-792, August 1973.
11. [KOR93] I. Koren, Computer Arithmetic Algorithms, Prentice Hall, Englewood Cliffs, New Jersey, 1993.
12. [NIC93] M. Nicolaidis, "Efficient Implementation of Self-Checking Adders and ALUs", Proc. 23th Fault Tolerant Computing Symposium, Toulouse France, June 1993.
13. [NIC97a] M. Nicolaidis, R.O. Duarte, S. Manich, and J. Figueras, "Achieving Fault Secureness in Parity Prediction Arithmetic Operators", To appear in IEEE Design &Test of Computers.
14. [NIC97b] Nicolaidis M., "Carry Checking Parity Prediction Adders and ALUs", submited to IEEE Trans. on VLSI Systems.
15. [NIC 98a] M. Nicolaidis, "Scaling Deeper to Submicron: On-Line Testing to the Rescue", In proceedings FTCS-28, pp. 299-301, June 1998, Munich.
16. [NIC 98b] M. Nicolaidis, "Design for Soft-Error Robustness to Rescue Deep Submicron Scaling", In proceedings ITC 98, October 1998, Washington DC.
17. [NIC 98c] M. Nicolaidis, " On-Line Testing for VLSI: State of the Art and Trends", Integration: the VLSI Journal, Elsevier, Special Issue on "VLSI Testing toward 21 Century", Autumn 1998.
18. [NIK88] D. Nikolos, A. M. Paschalis, and G. Philokyprou, "Efficient Design of Totally Self-Checking Checkers for all Low-Cost Arithmetic Codes", IEEE Trans. On Comput, vol. 37, No. 7, pp. 807-814, July 1988.
19. [PET72] W. W. Peterson, E. J. Weldon, Error-Correcting Codes, second Ed., The MIT press, Cambridge, Massachusetts, 1972.
20. [PIE94] S. J. Piestrak, "Design of Residue Generators and Multioperand Modular Adders Using Carry-Save Adders", IEEE Trans. On Comput, vol. 423, No. 1, pp. 68-77, Jan. 1994.
21. [SEL68] F. F. Sellers, M. Y. Hsiao and L. W. Bearnson, Error Detecting Logic for Digital Computers, New-York: Mc GRAWHILL 1968.
22. [SKl60] J. Sklansky, "Conditional-Sum Addition Logic", in IRE Transactions on Electronic Computers, Vol. EC-9, No. 2, pp 226-231, June 1960.
23. [SPA93] U. Sparmann, "On the Check Base Selection Problem for Fast Adders", Proc. 11th VLSI Test Symp. Atlantic City, NJ, April 1993.
24. [SPA94] U. Sparmann, S. M. Reddy. "On the Effectiveness of Residue Code Checking for Parallel Two's Complement Multipliers" Proc. 24th Fault Tolerant Computing Symposium, Austin Texas, June 1994.