Achieving fault secureness in parity prediction arithmetic operators: General conditions and implementations

Proceedings of the 1996 European Conference on Design and Test, EDTC 1996

Volumn , Issue , 1996, Pages 186-193

  Nicolaidis, M ^a   Manich, S ^b   Figueras, J ^b  

^a TIMA LABORATORY   (France)

^b UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

Author keywords

Arithmetic operators; Fault secure circuits; Parity prediction; Self checking circuits

Indexed keywords

COMPUTER CIRCUITS;

DATA PATHS; FAULT SECURE; MEMORY SYSTEMS; MULTIPLE OUTPUTS; PARITY CODES; PARITY PREDICTION; SELF CHECKING CIRCUITS; SINGLE FAULT;

FORECASTING;

EID: 85029658872     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EDTC.1996.494147     Document Type: Conference Paper

References (12)

1. Avizienis A., 'Arithmetic Algorithms for Error-Coded Operands' IEEE Trans. on Comput., Vol. C-22, No. 6, pp. 567-572, June 1973.
2. Furuya K., Akita Y., Tohma Y., "Logic design of Fault Tolerant Dividers based on Data complementation Strategy", 13th Intl Symp. Fault Tolerant Comp., Milan, Italy, June 1983.
3. Garcia O.N., Rao T.R.N., 'On the method of checking logical operations', Proc. 2nd Annual Princeton Conf. Inform. Sci. sys., pp. 89-95 (1968).
4. Hwang K., 'Computer Arithmetic, Principles, Architecture and Design', John Wiley and Sons, New-York, 1979.
5. Koren I., "Computer Arithmetic Algorithms", Prentice Hall, Englewood Cliffs, New Jersey, 1993.
6. Nicolaidis M. 'Efficient Implementation of Self-Checking Adders and ALUs'. Proc. 23th Fault Tolerant Computing Symposium, Toulouse France, June 1993.
7. Nicolaidis M. Bedder H. 'Efficient Implementation of Self-Checking Multiply and Divide Arrays'. Proc. 1994 European Design and Test Conference, Paris, February 28-March 3, 1994.
8. Peterson W.W., Weldon E.J., 'Error-Correcting Codes', second Ed., The MIT press, Cambridge, Massachusetts, 1972.
9. Pradhan D.K., "Fault Tolerant Computing, Theory and Techniques", Volume I, Prentice Hall, Englewood Cliffs, New Jersey, 1986.
10. Sellers F.F., Hsiao M.-Y. and Bearnson L.W., 'Error Detecting Logic for Digital Computers', New-York: Mc GRAW-HILL 1968.
11. Sparmann U. 'On the Check Base Selection Problem for Fast Adders' Proc. 11th VLSI Test Symposium, Atlantic City, NJ, April 1993.
12. Sparmann U. Reddy S.M. 'On the Effectiveness of Residue Code Checking for Parallel Two's Complement Multipliers' Proc. 24th Fault Tolerant Computing Symposium, Austin Texas, June 1994.