Low-pressure (< 5 MPa) low-temperature joining of large-area chips on copper using nanosilver paste

2012 7th International Conference on Integrated Power Electronics Systems, CIPS 2012

Volumn , Issue , 2012, Pages

  Zheng, Hanguang ^a,b   Calata, Jesus ^a,b   Ngo, Khai ^a,c   Luo, Susan ^d   Lu, Guo Quan ^b,c,e  

^a Center for Power Electronics Systems   (United States)

^b Department of Materials Science and Engineering ^*  (United States)

^c Virginia Polytechnic Institute and State University   (United States)

^d NBE Technologies LLC   (United States)

^e TIANJIN UNIVERSITY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

APPLYING PRESSURE; BONDING STRENGTH; JOINING TECHNOLOGY; LOW TEMPERATURES; NANO-SILVER PASTES; OXIDIZED SURFACES; PROCESSING CONDITION; SINTERING PRESSURE;

COPPER; JOINING; OXIDATION; SILVER; SINTERING; SUBSTRATES; TEMPERATURE; WIRE;

BONDING;

EID: 84881106516     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)

1. P. Beckedahl, et al., "A new power module concept for automotive applications," Proc. PCIM, Nuremberg, 2007.
2. W. Wondrak, et al., "SiC devices for advanced power and high-temperature applications," Industrial Electronics, IEEE Transactions on, vol. 48, pp. 307-308, 2001.
3. M. Abtew and G. Selvaduray, "Lead-free solders in microelectronics," Materials Science and Engineering: R: Reports, vol. 27, pp. 95-141, 2000.
4. H. Ma and J. C. Suhling, "A review of mechanical properties of lead-free solders for electronic packaging," Journal of materials science, vol. 44, pp. 1141-1158, 2009.
5. K. Stinson-Bagby, et al., "Thermal performance and microstructure of lead versus lead-free solder die attach interface in power device packages," Electronics and the Environment, 2004. Conference Record., pp. 27-32, 2004.
6. H. Schwarzbauer and R. Kuhnert, "Novel large area joining technique for improved power device performance," Industry Applications Society Annual Meeting, 1989., pp. 1348-1351 vol. 2, 1989.
7. J. G. Bai, et al., "Low-temperature sintered nanoscale silver as a novel semiconductor device-metallized substrate interconnect material," Components and Packaging Technologies, IEEE Transactions on, vol. 29, pp. 589-593, 2006.
8. J. G. Bai, et al., "Low-temperature sintered silver attachment for high-temperature operation of SiC power devices," in Proc. 4th Int. Conf. Integrated Power Electron. Syst. (CIPS '06), Naples, Italy, pp. 53-57.
9. T. G. Lei, et al., "Low-Temperature Sintering of Nanoscale Silver Paste for Attaching Large-Area(> 100 mm2) Chips," Components and Packaging Technologies, IEEE Transactions on, vol. 33, pp. 98-104, 2010.
10. X. Liu, et al., "Packaging of integrated power electronics modules using flip-chip technology," Applied Power Electronics Conference and Exposition, 2000., pp. 290-296 vol. 1, 2000.
11. Y. Yamada, et al., "Pb-free high temperature solders for power device packaging," Microelectronics Reliability, vol. 46, pp. 1932-1937, 2006.