Channel thickness effect on high-frequency performance of poly-Si thin-film transistors

IEEE Electron Device Letters

Volumn 34, Issue 8, 2013, Pages 1020-1022

  Chen, Kun Ming ^a   Tsai, Tzu I ^b   Lin, Ting Yao ^b   Lin, Horng Chih ^a,b   Chao, Tien Sheng ^b   Huang, Guo Wei ^a,b   Huang, Tiao Yuan ^b  

^a NATIONAL NANO DEVICE LABORATORIES   (Taiwan)

^b NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

Channel thickness; gate length; radio frequency; thin film transistors (TFTs); transconductance

Indexed keywords

CHANNEL THICKNESS; GATE LENGTH; HIGH FREQUENCY CHARACTERISTICS; MAXIMUM OSCILLATION FREQUENCY; POLY-SI THIN-FILM TRANSISTORS; POLYCRYSTALLINE SILICON (POLY-SI); RADIO FREQUENCIES; THIN-FILM TRANSISTOR (TFTS);

CUTOFF FREQUENCY; THIN FILM TRANSISTORS; TRANSCONDUCTANCE;

SILICON;

EID: 84881030468     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2013.2267809     Document Type: Article

References (17)

1. S. Zhang, C. Zhu, J. K. O. Sin, et al., "Ultra-thin elevated channel poly-Si TFT technology for fully-integrated AMLCD system on glass," IEEE Trans. Electron Devices, vol. 47, no. 3, pp. 569-575, Mar. 2000. (Pubitemid 30578389)
2. T. Serikawa, S. Shirai, A. Okamoto, et al., "Low-temperature fabrication of high-mobility poly-Si TFTs for large-area LCD's," IEEE Trans. Electron Devices, vol. 36, no. 9, pp. 1929-1933, Sep. 1989. (Pubitemid 20617837)
3. I.-C. Lee, T.-C. Tsai, C.-C. Tsai, et al., "Vertically-stacked bottom-and top-gate polycrystalline silicon TFTs for three dimensional integrated circuit," in Proc. IEEE Int. Nanoelectron. Conf., Jun. 2011, pp. 1-2.
4. E.-K. Lai, H.-T. Lue, Y.-H. Hsiao, et al., "A multi-layer stackable thinfilm transistor (TFT) NAND-type flash memory," in IEDM Tech. Dig., 2006, pp. 41-44.
5. N. Saputra, M. Danesh, A. Baiano, et al., "An assessment of ?-Czochralski, single-grain silicon thin-film transistor technology for large-area, sensor and 3-D electronic integration," IEEE J. Solid-State Circuits, vol. 43, no. 7, pp. 1563-1575, Jul. 2008.
6. J. L. Botrel, O. Savry, O. Rozeau, et al., "Polysilicon high frequency devices for large area electronics: Characterization, simulation and modeling," Thin Solid Films, vol. 515, no. 19, pp. 7422-7427, 2007. (Pubitemid 47198719)
7. Y.-J. E. Chen, Y.-J. Lee, and Y.-H. Yu, "Investigation of polysilicon thin-film transistor technology for RF application," IEEE Trans. Microw. Theory Tech., vol. 58, no. 12, pp. 3444-3451, Dec. 2010.
8. G. K. Giust and T. W. Sigmon, "High-performance thin-film transistors fabricated using excimer laser processing and grain engineering," IEEE Trans. Electron Devices, vol. 45, no. 4, pp. 925-932, Apr. 1998.
9. S. Y. Kim, W.-F. Loke, B. Jung, et al., "High-frequency modeling of poly-Si thin-film transistors for low-cost RF applications," IEEE Trans. Electron Devices, vol. 59, no. 9, pp. 2296-2301, Sep. 2012.
10. S. G. Shahidi, C. A. Anderson, B. A. Chappell, et al., "A room temperature CMOS on SOI," IEEE Trans. Electron Devices, vol. 41, no. 12, pp. 2405-2412, Dec. 1994.
11. J. Levinson, F. R. Shepherd, P. J. Scanlon, et al., "Conductivity behavior in polycrystalline semiconductor thin film transistors," J. Appl. Phys., vol. 53, no. 2, pp. 1193-1202, 1982. (Pubitemid 12476856)
12. T. W. Little, K. Takahara, H. Koike, et al., "Low temperature poly-Si TFTs using solid phase crystallization of very thin films and an electron cyclotron resonance chemical vapor deposition gate insulator," Jpn. J. Appl. Phys., vol. 30, no. 12B, pp. 3724-3728, Dec. 1991.
13. S. Luan and G. W. Neudeck, "An experimental study of the source/drain parasitic resistance effects in amorphous silicon thin film transistors, " J. Appl. Phys., vol. 72, no. 2, pp. 766-772, Jul. 1992.
14. K. Suzuki, T. Tanaka, Y. Tosaka, et al., "Source/drain contact resistance of silicided thin-film SOI MOSFET's," IEEE Trans. Electron Devices, vol. 41, no. 6, pp. 1007-1013, Jun. 1994.
15. C. Lavoie, C. Murray, C. D'Emic, et al., "Extendibility of NiPt silicide contacts for CMOS technology demonstrated to the 22-nm node," in IEDM Tech. Dig., 2007, pp. 1029-1031.
16. C.-H. Kuo, H.-C. Lin, I-C. Lee, et al., "A novel scheme for fabricating CMOS inverters with poly-Si nanowire channels," IEEE Electron Device Lett., vol. 33, no. 6, pp. 833-835, Jun. 2012.
17. D. Lovelace, J. Costa, and N. Camilleri, "Extracting small-signal model parameters of silicon MOSFET transistors," in Proc. IEEE MTT-S Int. Microw. Symp., May 1994, pp. 865-868.