-
1
-
-
64949106457
-
A novel architecture of the 3d stacked MRAM l2 cache for CMPs
-
G. Sun and et al, "A Novel Architecture of the 3D Stacked MRAM L2 Cache for CMPs, " in Proc. of HPCA, 2009, pp. 239-249.
-
(2009)
Proc. of HPCA
, pp. 239-249
-
-
Sun, G.1
-
2
-
-
79955889816
-
Relaxing non-volatility for fast and energy-efficient STT-RAM caches
-
C. Smullen and et al., "Relaxing Non-Volatility for Fast and Energy-Efficient STT-RAM Caches, " in Proc. of HPCA, 2011, pp. 50-61.
-
(2011)
Proc. of HPCA
, pp. 50-61
-
-
Smullen, C.1
-
4
-
-
70349268227
-
A 90nm 12ns 32Mb 2t1MTJ MRAM
-
R. Nebashi and et al, "A 90nm 12ns 32Mb 2T1MTJ MRAM, " in Conf. of ISSCC, 2009, pp. 462-463.
-
(2009)
Conf. of ISSCC
, pp. 462-463
-
-
Nebashi, R.1
-
5
-
-
77957956589
-
Combined magnetic-and circuit-level enhancements for the nondestructive self-reference scheme of STT-RAM
-
Y. Chen and et al, "Combined Magnetic-and Circuit-Level Enhancements for the Nondestructive Self-Reference Scheme of STT-RAM, " in Proc. of ISLPED, 2010, pp. 1-6.
-
(2010)
Proc. of ISLPED
, pp. 1-6
-
-
Chen, Y.1
-
6
-
-
84879871667
-
-
"Itrs, " http://www.itrs.net.
-
Itrs
-
-
-
7
-
-
76549097696
-
Racetrack memory: A storage class memory based on current controlled magnetic domain wall motion
-
S. Parkin, "Racetrack Memory: A Storage Class Memory Based on Current Controlled Magnetic Domain Wall Motion, " in DRC, 2009, pp. 3-6.
-
(2009)
DRC
, pp. 3-6
-
-
Parkin, S.1
-
8
-
-
79951958287
-
Observation of the intrinsic pinning of a magnetic domain wall in a ferromagnetic nanowire
-
T. Koyama and et al, "Observation of the Intrinsic Pinning of a Magnetic Domain Wall in a Ferromagnetic Nanowire, " Nat. Mat., vol. 10, no. 3, pp. 194-197, 2011.
-
(2011)
Nat. Mat.
, vol.10
, Issue.3
, pp. 194-197
-
-
Koyama, T.1
-
9
-
-
79951522055
-
Discrete domain wall positioning due to pinning in current driven motion along nanowires
-
X. Jiang and et al, "Discrete Domain Wall Positioning due to Pinning in Current Driven Motion along Nanowires, " Nano Lett., vol. 11, no. 1, pp. 96-100, 2010.
-
(2010)
Nano Lett.
, vol.11
, Issue.1
, pp. 96-100
-
-
Jiang, X.1
-
10
-
-
78650656670
-
Dynamics of magnetic domain walls under their own inertia
-
L. Thomas, R. Moriya, C. Rettner, and S. Parkin, "Dynamics of magnetic domain walls under their own inertia, " Science, vol. 330, no. 6012, pp. 1810-1813, 2010.
-
(2010)
Science
, vol.330
, Issue.6012
, pp. 1810-1813
-
-
Thomas, L.1
Moriya, R.2
Rettner, C.3
Parkin, S.4
-
11
-
-
71049160813
-
Low-current perpendicular domain wall motion cell for scalable high-speed mram
-
S. Fukami and et al, "Low-current perpendicular domain wall motion cell for scalable high-speed mram, " in Symp. on VLSI Technology, 2009, pp. 230-231.
-
(2009)
Symp. on VLSI Technology
, pp. 230-231
-
-
Fukami, S.1
-
12
-
-
84863024261
-
Racetrack memory cell array with integrated magnetic tunnel junction readout
-
A. Annunziata and et al, "Racetrack Memory Cell Array with Integrated Magnetic Tunnel Junction Readout, " in Symp.on IEDM, 2011, pp. 24-3.
-
(2011)
Symp.on IEDM
, pp. 24-33
-
-
Annunziata, A.1
-
13
-
-
80052658028
-
A content addressable memory using magnetic domain wall motion cells
-
R. Nebashi and et al, "A Content Addressable Memory using Magnetic Domain Wall Motion Cells, " in IEEE Symp. on VLSI Circuits, 2011, pp. 300-301.
-
(2011)
IEEE Symp. on VLSI Circuits
, pp. 300-301
-
-
Nebashi, R.1
-
14
-
-
84865546090
-
Tapecache: A high density, energy efficient cache based on domain wall memory
-
R. Venkatesan, and et al, "TapeCache: a High Density, Energy Efficient Cache based on Domain Wall Memory, " in Proc. of ISLPED, 2012, pp. 185-190.
-
(2012)
Proc. of ISLPED
, pp. 185-190
-
-
Venkatesan, R.1
-
15
-
-
84860155423
-
Current-induced torques in magnetic materials
-
A. Brataas and et al., "Current-induced torques in magnetic materials, " Nat. Mat., vol. 11, no. 5, pp. 372-381, 2012.
-
(2012)
Nat. Mat.
, vol.11
, Issue.5
, pp. 372-381
-
-
Brataas, A.1
-
16
-
-
84863355068
-
Multi retention level STT-RAM cache designs with a dynamic refresh scheme
-
Z. Sun. and et al., "Multi Retention Level STT-RAM Cache Designs with a Dynamic Refresh Scheme, " in Proc. of Micro, 2011, pp. 329-338.
-
(2011)
Proc. of Micro
, pp. 329-338
-
-
Sun, Z.1
-
17
-
-
84879849958
-
-
NVSim., "http://www.rioshering.com/nvsimwiki/index.php.".
-
NVSim
-
-
-
18
-
-
84879850112
-
-
Simics.,http://www.windriver.com/products/simics/
-
Simics
-
-
-
19
-
-
84879856664
-
-
Parsec., "http://parsec.cs.princeton.edu/index.htm.".
-
Parsec
-
-
|