A high-level synthesis flow for the implementation of iterative stencil loop algorithms on FPGA dewvices

Proceedings - Design Automation Conference

Volumn , Issue , 2013, Pages

  Nacci, Alessandro Antonio ^a   Rana, Vincenzo ^a   Bruschi, Francesco ^a   Sciuto, Donatella ^a   Beretta, Ivan ^b   Atienza, David ^b  

^a POLITECNICO DI MILANO   (Italy)

^b EPFL   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATIC GENERATION; DESIGN SPACE EXPLORATION; FPGA-HARDWARE IMPLEMENTATION; HARDWARE IMPLEMENTATIONS; HIGH LEVEL SYNTHESIS; ITERATIVE STENCIL LOOPS; MULTIPLE ITERATIONS; ORDERS OF MAGNITUDE;

ALGORITHMS; COMPUTER AIDED DESIGN; ITERATIVE METHODS;

HARDWARE;

EID: 84879864963     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2463209.2488797     Document Type: Conference Paper

References (25)

1. D. Crookes and K. Benkrid, "FPGA implementation of image component labelling", in Reconfigurable Technology: FPGAs for Computing and Applications, SPIE vol 3844, 17- 23 (1999).
2. K. Benkrid, S. Sukhsawas, D. Crookes, and A. Benkrid, "An FPGA-based image connected component labeller", in Field-Programmable Logic and Applications. Springer Berlin, 1012- 1015 (2003).
3. T. Pock et al., "A duality based algorithm for TV-L1 optical-flow image registration, " in Proc. of MICCAI, 2007, pp. 511-518.
4. J. Fowers at al., "A performance and energy comparison of FPGAs, GPUs, and multicores for sliding-window applications", in Proc. of FPGA '12, pp. 47-56.
5. M. Christen, "PATUS: A Code Generation and Autotuning Framework for Parallel Iterative Stencil Computations on Modern Microarchitectures", IPDPS 2011, pp. 676-687.
6. Z. Li and Y. Song, "Automatic tiling of iterative stencil loops", ACM Trans. Program. Lang. Syst. 26, Nov. 2004, pp. 975-1028.
7. J. Meng and K. Skadron, "Performance modeling and automatic ghost zone optimization for iterative stencil loops on GPUs.", ICS, 2009, pp. 256-265.
8. J. Meng and K. Skadron, "A Performance Study for Iterative Stencil Loops on GPUs with Ghost Zone Optimizations", International Journal of Parallel Programming, 2011, 39, pp. 115-142.
9. C. Alias et al., "Automatic generation of FPGA-specific pipelined accelerators, " in Proc. of ARC, 2011, pp. 53-66.
10. D. V. Rao et al., "Implementation and evaluation of image processing algorithms on reconfigurable architecture using c-based hardware descriptive languages, " JATIT, vol. 1, pp. 9-34, 2006.
11. Y. Park et al., "A new method of illumination normalization for robust face recognition, " in Progress in Pattern Recognition, Image Analysis and Applications, Springer, 2006, vol. 4225, pp. 38-47.
12. S. L. Park, "Retinex method based on cmsb-plane for variable lighting face recognition, " in Proc. of ICALIP, 2008, pp. 499 -503.
13. E. Jamro et al., "Convolution operation implemented in FPGA structures for real-time image processing, " in Proc. of ISPA, 2001, pp. 417-422.
14. C. Charoensak and F. Sattar, "A single-chip FPGA design for real-time ica-based blind source separation algorithm, " in Proc. of ISCAS, 2005, pp. 5822-5825, vol. 6.
15. K. Mohammad and S. Agaian, "Efficient FPGA implementation of convolution, " in Proc. of SMC, 2009, pp. 3478 -3483.
16. B. Cope, "Implementation of 2D Convolution on FPGA, GPU and CPU, " Master's thesis, Department of Electrical & Electronic Engineering, Imperial College London, 2006.
17. L. Gerard et al., "A Jacobi-Davidson Iteration Method for Linear Eigenvalue Problems, " SIAM Review, Vol. 42, No. 2, 2000, pp. 267-293.
18. A. Chambolle, "An algorithm for total variation minimization and applications, " Journal of Mathematical Imaging and Vision, vol. 20, pp. 89-97, 2004.
19. A. Akin et al., "A high-performance parallel implementation of the Chambolle algorithm, " in Proc. of DATE, 2011, pp.1-6.
20. V. Rana et al., "Design Methods for Parallel Hardware Implementation of Multimedia Iterative Algorithms, " IEEE Design & Test of Computers, 2012.
21. J. C. King, "Symbolic execution and program testing, " Commun. ACM, vol. 19, no. 7, pp. 385-394, 1976.
22. C. Zach et al., "A duality based approach for realtime TV-L1 optical flow, " DAGM conference on Pattern recognition, 2007, pp. 214-223.
23. A. Weishaupt et al., "Tracking and Structure from Motion, " Master's thesis, EPFL, 2010.
24. Synopsys, "Synphony C Compiler, " 2012.
25. Xilinx Inc., "Vivado Design Suite User Guide, High-Level Synthesis, " UG902, 2012.