Efficient FPGA implementation of convolution

Conference Proceedings - IEEE International Conference on Systems, Man and Cybernetics

Volumn , Issue , 2009, Pages 3478-3483

  Mohammad, Khader ^a   Agaian, Sos ^a  

^a University of Texas at San Antonio   (United States)

Author keywords

Convolution; Design and implementation for discrete linear convolution; FPGA; Implementations; Verilog

Indexed keywords

BUILDING BLOCKES; DESIGN APPROACHES; DIRECT METHOD; EXPANDABILITY; FINITE-LENGTH SEQUENCE; FPGA IMPLEMENTATIONS; HARDWARE COMPUTING; HARDWARE RESOURCES; HIERARCHICAL DESIGN; IMPLEMENTATION METHODS; LINEAR CONVOLUTION; POWER CONSUMPTION; PROCESSING TIME; REAL TIME; VERILOG;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CYBERNETICS; DESIGN; DIGITAL SIGNAL PROCESSING; FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

CONVOLUTION;

EID: 74849099936     PISSN: 1062922X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICSMC.2009.5346737     Document Type: Conference Paper

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