-
2
-
-
79953221591
-
-
Impulse-C, http://www.impulseaccelerated.com
-
Impulse-C
-
-
-
8
-
-
34547983276
-
Bee+Cl@k: An implementation of lattice-based memory reuse in the source-to-source translator ROSE
-
Alias, C., Baray, F., Darte, A.: Bee+Cl@k: An implementation of lattice-based memory reuse in the source-to-source translator ROSE. In: ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems, LCTES (2007)
-
ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems, LCTES (2007)
-
-
Alias, C.1
Baray, F.2
Darte, A.3
-
9
-
-
77955910338
-
Optimizing DDR-SDRAM communications at C-level for automatically- generated hardware accelerators. An experience with the Altera C2H HLS tool
-
Alias, C., Darte, A., Plesco, A.: Optimizing DDR-SDRAM communications at C-level for automatically-generated hardware accelerators. An experience with the Altera C2H HLS tool. In: IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP (2010)
-
IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP (2010)
-
-
Alias, C.1
Darte, A.2
Plesco, A.3
-
11
-
-
35048899223
-
Putting polyhedral loop transformations to work
-
Rauchwerger, L. (ed.) LCPC 2003. Springer, Heidelberg
-
Bastoul, C., Cohen, A., Girbal, S., Sharma, S., Temam, O.: Putting polyhedral loop transformations to work. In: Rauchwerger, L. (ed.) LCPC 2003. LNCS, vol. 2958, pp. 209-225. Springer, Heidelberg (2004)
-
(2004)
LNCS
, vol.2958
, pp. 209-225
-
-
Bastoul, C.1
Cohen, A.2
Girbal, S.3
Sharma, S.4
Temam, O.5
-
12
-
-
57349139452
-
A practical automatic polyhedral parallelizer and locality optimizer
-
Bondhugula, U., Hartono, A., Ramanujam, J., Sadayappan, P.: A practical automatic polyhedral parallelizer and locality optimizer. In: ACM International Conference on Programming Languages Design and Implementation, PLDI (2008)
-
ACM International Conference on Programming Languages Design and Implementation, PLDI (2008)
-
-
Bondhugula, U.1
Hartono, A.2
Ramanujam, J.3
Sadayappan, P.4
-
14
-
-
0029717349
-
Counting solutions to linear and nonlinear constraints through Ehrhart polynomials: Applications to analyze and transform scientific programs
-
Clauss, P.: Counting solutions to linear and nonlinear constraints through Ehrhart polynomials: Applications to analyze and transform scientific programs. In: ACM International Conference on Supercomputing, ICS (1996)
-
ACM International Conference on Supercomputing, ICS (1996)
-
-
Clauss, P.1
-
15
-
-
79953188474
-
A flexible floating-point logarithm for reconfigurable computers
-
ENS-Lyon
-
de Dinechin, F.: A flexible floating-point logarithm for reconfigurable computers. Lip research report RR2010-22, ENS-Lyon (2010), http://prunel.ccsd. cnrs.fr/ensl-00506122/
-
(2010)
Lip Research Report RR2010-22
-
-
De Dinechin, F.1
-
16
-
-
79951729454
-
Multiplicative square root algorithms for FPGAs
-
IEEE, Los Alamitos
-
de Dinechin, F., Joldes, M., Pasca, B., Revy, G.: Multiplicative square root algorithms for FPGAs. In: Field Programmable Logic and Applications. IEEE, Los Alamitos (2010)
-
(2010)
Field Programmable Logic and Applications
-
-
De Dinechin, F.1
Joldes, M.2
Pasca, B.3
Revy, G.4
-
17
-
-
70450043135
-
Generating high-performance custom floating-point pipelines
-
IEEE, Los Alamitos
-
de Dinechin, F., Klein, C., Pasca, B.: Generating high-performance custom floating-point pipelines. In: Field Programmable Logic and Applications. IEEE, Los Alamitos (2009)
-
(2009)
Field Programmable Logic and Applications
-
-
De Dinechin, F.1
Klein, C.2
Pasca, B.3
-
18
-
-
79551534454
-
Floating-point exponential functions for DSP-enabled FPGAs
-
IEEE, Los Alamitos
-
de Dinechin, F., Pasca, B.: Floating-point exponential functions for DSP-enabled FPGAs. In: Field Programmable Technologies. IEEE, Los Alamitos (2010), http://prunel.ccsd.cnrs.fr/ensl-00506125/
-
(2010)
Field Programmable Technologies
-
-
De Dinechin, F.1
Pasca, B.2
-
19
-
-
78650423490
-
An FPGA-specific approach to floating-point accumulation and sum-of-products
-
IEEE, Los Alamitos
-
de Dinechin, F., Pasca, B., Creţ, O., Tudoran, R.: An FPGA-specific approach to floating-point accumulation and sum-of-products. In: Field-Programmable Technologies. IEEE, Los Alamitos (2008)
-
(2008)
Field-Programmable Technologies
-
-
De Dinechin, F.1
Pasca, B.2
Creţ, O.3
Tudoran, R.4
-
20
-
-
20344376214
-
64-bit floating-point fpga matrix multiplication
-
Dou, Y., Vassiliadis, S., Kuzmanov, G.K., Gaydadjiev, G.N.: 64-bit floating-point fpga matrix multiplication. In: ACM/SIGDA symposium on Field-Programmable Gate Arrays, FPGA (2005)
-
ACM/SIGDA Symposium on Field-Programmable Gate Arrays, FPGA (2005)
-
-
Dou, Y.1
Vassiliadis, S.2
Kuzmanov, G.K.3
Gaydadjiev, G.N.4
-
21
-
-
0001023389
-
Parametric integer programming
-
Feautrier, P.: Parametric integer programming. RAIRO Recherche Opérationnelle 22(3), 243-268 (1988)
-
(1988)
RAIRO Recherche Opérationnelle
, vol.22
, Issue.3
, pp. 243-268
-
-
Feautrier, P.1
-
22
-
-
84941358063
-
Spark: A high-level synthesis framework for applying parallelizing compiler transformations
-
Gupta, S., Dutt, N., Gupta, R., Nicolau, A.: Spark: A high-level synthesis framework for applying parallelizing compiler transformations. In: International Conference on VLSI Design (2003)
-
International Conference on VLSI Design (2003)
-
-
Gupta, S.1
Dutt, N.2
Gupta, R.3
Nicolau, A.4
-
25
-
-
0027812462
-
Gaut: An architectural synthesis tool for dedicated signal processors
-
Martin, E., Sentieys, O., Dubois, H., Philippe, J.L.: Gaut: An architectural synthesis tool for dedicated signal processors. In: Design Automation Conference with EURO-VHDL 1993, EURO-DAC (1993)
-
Design Automation Conference with EURO-VHDL 1993, EURO-DAC (1993)
-
-
Martin, E.1
Sentieys, O.2
Dubois, H.3
Philippe, J.L.4
-
27
-
-
0442303278
-
-
Kluwer Academic Publishers, Dordrecht
-
Xue, J.: Loop Tiling for Parallelism. Kluwer Academic Publishers, Dordrecht (2000)
-
(2000)
Loop Tiling for Parallelism
-
-
Xue, J.1
|