HaDeS: Architectural synthesis for heterogeneous dark silicon chip multi-processors

Proceedings - Design Automation Conference

Volumn , Issue , 2013, Pages

  Turakhia, Yatish ^a   Raghunathan, Bharathwaj ^b   Garg, Siddharth ^b   Marculescu, Diana ^c  

^a INDIAN INSTITUTE OF TECHNOLOGY BOMBAY   (India)

^b UNIVERSITY OF WATERLOO   (Canada)

^c CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION PERFORMANCE; ARCHITECTURAL SYNTHESIS; CHIP MULTI-PROCESSORS (CMPS); DEGREE OF PARALLELISM; HETEROGENEOUS CMPS; ITERATIVE OPTIMIZATION; MULTI-THREADED APPLICATION; PERFORMANCE IMPROVEMENTS;

COMPUTER AIDED DESIGN; OPTIMIZATION;

SILICON;

EID: 84879855425     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2463209.2488948     Document Type: Conference Paper

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