Register and thread structure optimization for GPUs

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2013, Pages 461-466

  Liang, Yun ^a   Cui, Zheng ^b   Rupnow, Kyle ^b,c   Chen, Deming ^b,d  

^a PEKING UNIVERSITY   (China)

^b ADVANCED DIGITAL SCIENCES CENTER   (Singapore)

^c NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

^d UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN SPACE EXPLORATION; EFFICIENT DESIGN SPACE EXPLORATIONS; HIGH PERFORMANCE COMPUTING; IMPLEMENTATION PLATFORMS; OPTIMIZATION TECHNIQUES; PARALLEL PROGRAMMING MODEL; SINGLE-THREAD PERFORMANCE; STRUCTURE OPTIMIZATION;

COMPUTER AIDED DESIGN; PROGRAM PROCESSORS;

STRUCTURAL OPTIMIZATION;

EID: 84877777934     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2013.6509639     Document Type: Conference Paper

References (14)

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