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Volumn 56, Issue , 2013, Pages 158-159

A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS

Author keywords

[No Author keywords available]

Indexed keywords

EXTERNAL MEMORY; FRAME BUFFER; H.264 ENCODERS; LOW-POWER TECHNOLOGY; ON-CHIP PERIPHERALS; ULTRA-LOW POWER; ULTRA-LOW-VOLTAGE; VOLTAGE-SCALING;

EID: 84876558313     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2013.6487680     Document Type: Conference Paper
Times cited : (19)

References (5)
  • 1
    • 70349282148 scopus 로고    scopus 로고
    • A 212mpixels/s 4096?2160p multi-view video encoder chip for 3d/quad hdtv applications
    • L. F. Ding, et al., "A 212Mpixels/s 4096?2160p Multi-View Video Encoder Chip for 3D/Quad HDTV Applications," ISSCC Dig. Tech. Papers, pp. 154-155, 2009.
    • (2009) ISSCC Dig. Tech. Papers , pp. 154-155
    • Ding, L.F.1
  • 2
    • 2442716234 scopus 로고    scopus 로고
    • A 180mv fft processor using subthreshold circuit techniques
    • A. Wang, et al., "A 180mV FFT Processor Using Subthreshold Circuit Techniques," ISSCC Dig. Tech. Papers, pp. 292-293, 2004.
    • (2004) ISSCC Dig. Tech. Papers , pp. 292-293
    • Wang, A.1
  • 3
    • 85008054031 scopus 로고    scopus 로고
    • A 256kb 65nm 8t subthreshold sram employing sense-amplifier redundancy
    • N. Verma and A. P. Chandrakasan, "A 256Kb 65nm 8T Subthreshold SRAM Employing Sense-Amplifier Redundancy," IEEE J. Solid-State Circuits, vol. 43, no. 1, pp. 141-149, 2008.
    • (2008) IEEE J. Solid-State Circuits , vol.43 , Issue.1 , pp. 141-149
    • Verma, N.1    Chandrakasan, A.P.2
  • 4
    • 33645652998 scopus 로고    scopus 로고
    • A self-tuning dvs processor using delay-error detection and correction
    • S. Das, et al., "A Self-Tuning DVS Processor Using Delay-Error Detection and Correction," IEEE J. Solid-State Circuits, vol. 41, no. 4, pp. 792-804, 2006.
    • (2006) IEEE J. Solid-State Circuits , vol.41 , Issue.4 , pp. 792-804
    • Das, S.1
  • 5
    • 77954480374 scopus 로고    scopus 로고
    • Collaborative voltage scaling with online sta and variable-latency datapath
    • T. J. Lin, et al., "Collaborative Voltage Scaling with Online STA and Variable-Latency Datapath," IEEE Great Lakes Symp. VLSI, pp. 347-352, 2010.
    • (2010) IEEE Great Lakes Symp. VLSI , pp. 347-352
    • Lin, T.J.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.