A 212MPixels/s 4096×2160p multiview video encoder chip for 3D/Quad HDTV applications

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2009, Pages

  Ding, Li Fu ^a   Chen, Wei Yin ^a   Tsung, Pei Kuei ^a   Chuang, Tzu Der ^a   Chiu, Hsu Kuang ^a   Chen, Yu Han ^a   Hsiao, Pai Heng ^a   Chien, Shao Yi ^a   Chen, Tung Chien ^a   Lin, Ping Chih ^a   Chang, Chia Yu ^a   Chen, Liang Gee ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 70349282148     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2009.4977354     Document Type: Conference Paper

References (4)

1. Joint Video Team of ISO/IEC MPEG & ITU-T VCEG, "Joint Draft 7.0 on Multiview Video Coding," ISO/IEC JTC1/SC29/WG11 and ITU-T SG16 Q.6, April 2008.
2. Y. W. Huang, et al., "A 1.3TOPS H.264/AVC Single-Chip Encoder for HDTV applications," ISSCC Dig. Tech. Papers, pp. 128-129, Feb. 2005.
3. H. C. Chang, et al., "A 7mW to 183mW Dynamic Quality-Scalable H.264 Video Encoder Chip," ISSCC Dig. Tech. Papers, pp. 280-281, Feb. 2007.
4. 2 1080p H.264/AVC High-Profile Encoder Chip," ISSCC Dig. Tech. Papers, pp. 314-315, Feb. 2008.