A scalable 0.128-to-1Tb/s 0.8-to-2.6pJ/b 64-lane parallel I/O in 32nm CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 56, Issue , 2013, Pages 402-403

  Mansuri, Mozhgan ^a   Jaussi, James E ^a   Kennedy, Joseph T ^a   Hsueh, Tzu Chien ^a   Shekhar, Sudip ^a   Balamurugan, Ganesh ^a   O'Mahony, Frank ^a   Roberts, Clark ^a   Mooney, Randy ^a   Casper, Bryan ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AGGRESSIVE SCALING; DESIGN ROBUSTNESS; HIGH PERFORMANCE COMPUTING SYSTEMS; INTERCONNECT DENSITIES; POWER EFFICIENCY; POWER SCALABLE; RECONFIGURABLE; SUPPLY-VOLTAGE SCALING;

ACTIVE FILTERS; BANDWIDTH; EFFICIENCY; FAULT TOLERANCE;

AGGREGATES;

EID: 84876532873     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2013.6487788     Document Type: Conference Paper

References (6)

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2. M. Mansuri, et al., "An On-Die All-Digital Delay Measurement Circuit with 250fs Accuracy," Symp. VLSI Circuits Dig. Tech. Papers, pp. 98-99, Jun. 2012
3. A. Amirkhani, et al., "A 4.1pJ/b 16Gb/s Coded Differential Bidirectional Parallel Electrical Link," ISSCC Dig. Tech. Papers, pp. 138-139, Feb. 2012
4. K. Kaviani, et al., "A Tri-Modal 20-Gbs/Link Differential/DDR3/GDDR5 Memory Interface," IEEE J. Solid-State Circuits, vol. 47, no. 4, pp. 926-937, Apr. 2012
5. H. Lee, et al., "A 16Gb/s/Link, 64GB/s Bidirectional Asymmetric Memory interface," IEEE J. Solid-State Circuits, vol. 44, no. 4, pp. 1235-1247, Apr. 2009
6. K. Fukuda, et al., "A 12.3mW 12.5Gb/s Complete Transceiver in 65nm CMOS," ISSCC Dig. Tech. Papers, pp. 368-369, Feb. 2010