A 4.1pJ/b 16Gb/s coded differential bidirectional parallel electrical link

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 55, Issue , 2012, Pages 138-139

  Amirkhany, Amir ^a   Kaviani, Kambiz ^a   Abbasfar, Aliazam ^a   Shuaeb, Fazeel ^b   Beyene, Wendem ^a   Hoshino, Chikara ^c   Madden, Chris ^a   Chang, Ken ^a   Yuan, Chuck ^a  

^a Rambus   (United States)

^b Rambus IDC   (India)

^c Rambus   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DECISION-FEEDBACK EQUALIZATIONS; DIFFERENTIAL SIGNALING; FOUR-WIRE; HIGH-SPEED; LOW LEVEL; REFERENCE VOLTAGES; SWITCHING NOISE;

WIRE;

SIGNALING;

EID: 84860655320     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2012.6176953     Document Type: Conference Paper

References (5)

1. pp voltage-mode driver," ISSCC Dig. Tech. Papers, pp.350-351, Feb. 2011.
2. S. Quan, F. Zhong, et al, "A 1.0625-to-14.025Gb/s multimedia transceiver with full-rate source-series-terminated transmit driver and floating-tap decision-feedback equalizer in 40nm CMOS," ISSCC Dig. Tech. Papers, pp. 348-350, Feb. 2011.
3. V. Stojanovic, et al, "Autonomous dual-mode (PAM2/4) serial link transceiver with adaptive equalization and data recovery," IEEE J. of Solid-State Circuits, April 2005.
4. K. Kaviani, et al., "A 0.4mW/Gb/s 16Gb/s near-ground receiver front-end with replica transconductance termination calibration," ISSCC Dig. Tech Papers, pp. 132-133, Feb. 2012.
5. K. Kaviani, et al., "A tri-modal 20Gb/s/link differential/DDR3/GDDR5 memory interface," VLSI Circuits Symposium, June 2011.