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Volumn 1800 LNCS, Issue , 2000, Pages 186-193

Advanced data layout optimization for multimedia applications

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EID: 84876354818     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-45591-4_25     Document Type: Conference Paper
Times cited : (8)

References (16)
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    • July
    • P.Baglietto, M.Maresca and M.Migliardi, "Image processing on high-performance RISC systems", Proc. of the IEEE, vol. 84, no. 7, pp.917-929, July 1996.
    • (1996) Proc. of the IEEE , vol.84 , Issue.7 , pp. 917-929
    • Baglietto, P.1    Maresca, M.2    Migliardi, M.3
  • 6
    • 0033075413 scopus 로고    scopus 로고
    • Improving cache locality by a combination of loop and data transformations
    • M.Kandemir, J.Ramanujam, A.Choudhary, "Improving cache locality by a combination of loop and data transformations", IEEE trans, on computers, vol. 48, no. 2, pp. 159-167, 1999.
    • (1999) IEEE Trans, on Computers , vol.48 , Issue.2 , pp. 159-167
    • Kandemir, M.1    Ramanujam, J.2    Choudhary, A.3
  • 7
    • 0031701130 scopus 로고    scopus 로고
    • Code transformations for low power caching in embedded multimedia processors
    • Orlando FL, April
    • C.Kulkarni, F.Catthoor, H.De Man, "Code transformations for low power caching in embedded multimedia processors,", Intnl. Parallel Proc. Symp.(IPPS/SPDP), Orlando FL, pp.292-297,April 1998.
    • (1998) Intnl. Parallel Proc. Symp.(IPPS/SPDP) , pp. 292-297
    • Kulkarni, C.1    Catthoor, F.2    De Man, H.3
  • 8
    • 0029304656 scopus 로고
    • Linear loop transformations in optimizing compilers for parallel machines
    • may
    • D.Kulkarni and M.Stumm, "Linear loop transformations in optimizing compilers for parallel machines". The Australian computer journal, pp.41-50, may 1995.
    • (1995) The Australian Computer Journal , pp. 41-50
    • Kulkarni, D.1    Stumm, M.2
  • 14
    • 84876385341 scopus 로고    scopus 로고
    • Memory data organization for improved cache performance in embedded processor applications
    • La Jolla, Ca., Nov.
    • P.R.Panda, N.D.Dutt and A.Nicolau, " Memory data organization for improved cache performance in embedded processor applications". In Proc. ISSS-96, pp.9095, La Jolla, Ca., Nov 1996.
    • (1996) Proc. ISSS-96 , pp. 9095
    • Panda, P.R.1    Dutt, N.D.2    Nicolau, A.3
  • 15
    • 0033076195 scopus 로고    scopus 로고
    • Augmented loop tiling with data alignment for improved cache performance
    • P.R.Panda, H.Nakamura, N.D.Dutt and A.Nicolau, "Augmented loop tiling with data alignment for improved cache performance", IEEE trans, on computers, vol. 48, no. 2, pp. 142-149, 1999.
    • (1999) IEEE Trans, on Computers , vol.48 , Issue.2 , pp. 142-149
    • Panda, P.R.1    Nakamura, H.2    Dutt, N.D.3    Nicolau, A.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.