ZIP-IO: Architecture for application-specific compression of Big Data

FPT 2012 - 2012 International Conference on Field-Programmable Technology

Volumn , Issue , 2012, Pages 343-351

  Jun, Sang Woo ^a   Fleming, Kermin E ^a   Adler, Michael ^b   Emer, Joel ^a,b  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIG DATUM; COMPRESSION ALGORITHMS; INDUSTRIAL SOFTWARE; ITS DATA; LARGE DATASETS; WORKING SET;

ALGORITHMS; APPLICATION PROGRAMS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

DATA COMPRESSION;

EID: 84874075485     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPT.2012.6412159     Document Type: Conference Paper

References (25)

1. "Facebook newsroom." [Online]. Available: http://newsroom.fb. com
2. "Leap FPGA OS." [Online]. Available: http://asim.csail.mit.edu/ redmine/projects/show/leap
3. "MIPS IV Instruction Set." [Online]. Available: http://techpubs.sgi.com/library/manuals/2000/007-2597-001/pdf/007-2597-001.pdf
4. "Standard Performance Evaluation Corporation," http://www.spec.org.
5. "The Secret Sauce: 0.5x Write Amplification," 2009. [Online]. Available: http://www.anandtech.com/show/2899/3
6. K. C. Barr and K. Asanovi, "Branch trace compression for snapshot-based simulation," in In International Symposium on Performance Analysis of Systems and Software, 2006.
7. G. Beskales, M. Fontoura, M. Gurevich, S. Vassilvitskii, and V. Josifovski, "Factorization-based Lossless Compression of Inverted Indices," in Proceedings of the 20th ACM international conference on Information and knowledge management, ser. CIKM '11. New York, NY, USA: ACM, 2011, pp. 327-332. [Online]. Available: http://doi.acm.org/10.1145/2063576. 2063628
8. I.-T. V. C. E. Group, "Draft ITU-T Recommendation and Final Draft International Standard of Joint Video Specification," May, 2003.
9. J. Edler and M. D. Hill, "Dinero IV Trace-Driven Uniprocessor Cache Simulator." [Online]. Available: http://pages.cs.wisc.edu/markhill/ DineroIV/
10. A. Jaleel, R. S. Cohn, C. K. Luk, and B. Jacob, "Cmp$im: A Binary Instrumentation Approach to Modeling Memory Behavior of Workloads on CMPs," Tech. Rep., 2006.
11. Johnson, Eric E. and Ha, Jiheng and Zaidi, M. Baqar, "Lossless Trace Compression," IEEE Trans. Comput., pp. 158-173, Feb. 2001.
12. S. Kanev and R. Cohn, "Portable Trace Compression Through Instruction Interpretation," in ISPASS, 2011, pp. 107-116.
13. C. Kozanitis, C. Saunders, S. Kruglyak, V. Bafna, and G. Varghese, "Compressing Genomic Sequence Fragments Using SlimGene," in International Conference on Research in Molecular Biology, 2010.
14. S. Lee, J. Park, K. Fleming, Arvind, and J. Kim, "Improving Performance and Lifetime of Solid-state Drives Using Hardware-accelerated Compression," Trans. on Consumer Electronics, vol. 57, no. 4, pp. 1732-1739, november 2011.
15. Microsoft Corporation, "NTFS Technical Reference," 2011. [Online]. Available: http://technet.microsoft.com/enus/library/cc758691%28WS. 10%29.aspx
16. Milenković, Aleksandar and Milenković, Milena, "An efficient single-pass trace compression technique utilizing instruction streams," ACM Trans. Model. Comput. Simul., vol. 17, no. 1, Jan. 2007.
17. Nallatech, "Intel Xeon FSB FPGA Socket Fillers," http://www.nallatech.com/intel-xeon-fsb-fpga-socket-fillers.html.
18. A. Parashar, M. Adler, K. Fleming, M. Pellauer, and J. Emer, "LEAP: A Virtual Platform Architecture for FPGAs," in CARL '10: The 1st Workshop on the Intersections of Computer Architecture and Reconfigurable Logic, 2010.
19. A. Parashar, M. Adler, M. Pellauer, and J. Emer, "Hybrid CPU/FPGA Performance Models," in 3rd Workshop on Architectural Research Prototyping (WARP 2008), June 2008.
20. Red Hat Corporation, "JFFS2: The Journalling Flash File System," 2001. [Online]. Available: http://sources.redhat.com/jffs2/jffs2. pdf
21. H. So and R. W. Brodersen, "File system access from reconfigurable FPGA hardware processes in BORPH," in FPL, 2008, pp. 567-570.
22. H. So and R. Brodersen, "Improving Usability of FPGA-Based Reconfigurable Computers Through Operating System Support," in Field Programmable Logic and Applications, 2006. FPL '06. International Conference on, 2006, pp. 1 -6.
23. R. Tremaine, P. Franaszek, J. Robinson, C.Schulz, T. Smith, M. Wazowski, and P. Bland, "IBM Memory Expansion Technology," in IBM Journal of Research and Developement, 2001.
24. R. E. Wunderlich, T. F. Wenisch, B. Falsafi, and J. C. Hoe, "SMARTS: Accelerating Microarchitecture Simulation via Rigorous Statistical Sampling," in ISCA, 2003.
25. J. Ziv and A. Lempel, "A Universal Algorithm for Sequential Data Compression," IEEE Transactions on Information Theory, vol. 23, no. 3, pp. 337-343, 1977.