A closed-form expression for estimating minimum operating voltage (V DDmin) of CMOS logic gates

Proceedings - Design Automation Conference

Volumn , Issue , 2011, Pages 984-989

  Fuketa, Hiroshi ^a   Iida, Satoshi ^a   Yasufuku, Tadashi ^a   Takamiya, Makoto ^a   Nomura, Masahiro ^b   Shinohara, Hirofumi ^b   Sakurai, Takayasu ^a  

^a INSTITUTE OF INDUSTRIAL SCIENCE   (Japan)

^b SEMICONDUCTOR TECHNOLOGY ACADEMIC RESEARCH CENTER   (Japan)

Author keywords

Minimum operating voltage; subthreshold circuits; variations

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; INTELLIGENT SYSTEMS; LOGIC GATES; MONTE CARLO METHODS; THRESHOLD VOLTAGE;

CLOSED-FORM EXPRESSION; NMOS TRANSISTORS; OPERATING VOLTAGE; STANDARD DEVIATION; SUB-THRESHOLD CIRCUITS; VARIATIONS; VOLTAGE DIFFERENCE; WITHIN-DIE VARIATIONS;

COMPUTER CIRCUITS;

EID: 80052658521     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2024724.2024942     Document Type: Conference Paper

References (7)

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