20 GHz operation of an asynchronous wave-pipelined RSFQ arithmetic-logic unit

Physics Procedia

Volumn 36, Issue , 2012, Pages 59-65

  Filippov, Timur V ^a   Sahu, Anubhav ^a   Kirichenko, Alex F ^a   Vernik, Igor V ^a   Dorojevets, Mikhail ^b   Ayala, Christopher L ^b   Mukhanov, Oleg A ^a  

^a HYPRES INC   (United States)

^b Stony Brook University   (United States)

Author keywords

A lu; Datapath; Microprocessor; RSFQ

Indexed keywords

INTEGRATED CIRCUIT DESIGN; MICROPROCESSOR CHIPS; PIPELINE PROCESSING SYSTEMS; RECONFIGURABLE HARDWARE;

ARITHMETIC LOGIC UNIT; ASYNCHRONOUS WAVES; CRITICAL COMPONENT; DATA PATHS; HIGH FREQUENCY HF; INPUT AND OUTPUTS; PROCESSOR DATAPATH; RSFQ;

COMPUTER CIRCUITS;

EID: 84870792887     PISSN: 18753884     EISSN: 18753892     Source Type: Conference Proceeding    
DOI: 10.1016/j.phpro.2012.06.130     Document Type: Conference Paper

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