S/390 Parallel Enterprise Server Generation 3: A balanced system and cache structure

IBM Journal of Research and Development

Volumn 41, Issue 4-5, 1997, Pages 405-427

  Doettling, G ^a   Getzlaff, K J ^a   Leppla, B ^a   Lipponer, W ^a   Pflueger, T ^a   Schlipf, T ^a   Schmunkamp, D ^a   Wille, U ^a  

^a NONE

Author keywords

[No Author keywords available]

Indexed keywords

BIPOLAR INTEGRATED CIRCUITS; BUFFER STORAGE; CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE;

SYSTEM ASSIST PROCESSORS (SAP);

PARALLEL PROCESSING SYSTEMS;

EID: 0031177427     PISSN: 00188646     EISSN: None     Source Type: Journal    
DOI: 10.1147/rd.414.0405     Document Type: Article

References (13)

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