Low power Wallace multiplier design based on wide counters

International Journal of Circuit Theory and Applications

Volumn 40, Issue 11, 2012, Pages 1175-1185

  Abed, Sa'Ed ^a   Mohd, Bassam Jamil ^a   Al Bayati, Zaid ^b   Alouneh, Sahel ^c  

^a HASHEMITE UNIVERSITY   (Jordan)

^b Dept of Electrical and Computer Engineering   (Canada)

^c GERMAN JORDANIAN UNIVERSITY   (Jordan)

Author keywords

counters; low power multiplier; Wallace tree

Indexed keywords

A-CENTER; ARITHMETIC OPERATIONS; BATTERY LIFETIME; CHIP DESIGNERS; CIRCUIT DESIGN TECHNIQUES; CRITICAL PATHS; DIGITAL APPLICATIONS; GATE COUNT; HIGH-ORDER; LOW POWER; LOW POWER MULTIPLIERS; MULTIPLIER DESIGN; MULTIPLIER TREES; NUMBER OF GATES; PORTABLE APPLICATIONS; POWER CONSTRAINTS; POWER DENSITIES; POWER REDUCTIONS; POWER-AWARE; POWER-DELAY PRODUCTS; WALLACE TREE;

ALGORITHMS; FORESTRY; LOW POWER ELECTRONICS; PIPELINE PROCESSING SYSTEMS; PROGRAM PROCESSORS; RADIATION COUNTERS; SIGNAL PROCESSING; TREES (MATHEMATICS);

PRODUCT DESIGN;

ALGORITHMS; FORESTRY; MATHEMATICS; PRODUCT DESIGN; TREES;

EID: 84867673199     PISSN: 00989886     EISSN: 1097007X     Source Type: Journal    
DOI: 10.1002/cta.779     Document Type: Article

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