Novel architectures for efficient (m, n) parallel counters

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Volumn , Issue , 2007, Pages 188-191

  Veeramachaneni, Sreehari ^a   Lingamneni, Avinash ^a   Krishna, M Kirthi ^a   Srinivas, M B ^a  

^a INTERNATIONAL INSTITUTE OF INFORMATION TECHNOLOGY   (India)

Author keywords

High speed; Low power; Multiplexer; Parallel counters

Indexed keywords

CMOS INTEGRATED CIRCUITS; DIGITAL ARITHMETIC; ELECTRIC POWER UTILIZATION; INTEGRATED CIRCUIT LAYOUT; LOGIC GATES; MULTIPLEXING EQUIPMENT; PARALLEL ALGORITHMS;

ARITHMETIC CIRCUITS; PARALLEL COUNTERS; TRANSMISSION GATE LOGIC;

COUNTING CIRCUITS;

EID: 34748856443     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1228784.1228833     Document Type: Conference Paper

References (7)

1. LDadda, "Some Schemes for Parallel Multipliers," Alta Frequenza, Vol.34, pp.349-356, 1965.
2. th Annual International Phoenix Conference on Computers and Communications, pp.722-728,1992.
3. Earl E. Swartzlander, Jr., "A review of large parallel counter designs," Proceedings. IEEE Computer society Annual Symposium on VLSI, 2004, pp.89-98, Feb. 2004.
4. Earl E. Swartzlander, Jr., "Parallel Counters," IEEE Transactions on computers, Vol C-22, pp. 1021-1024, Nov. 1973.
5. Robert F. Jones, Jr., and Earl E. Swartzlander, Jr., "Parallel Counter implementation" Journal of VLSI signal processing, vol. 7, pp. 223-232, 1994.
6. Mayur Mehta, Vijay Parmar and Earl E. Swartzlander, Jr., "High-speed Multiplier Design using Multi-Input Counter and Compressor Circuits," Proceedings 10t Symposium on Computer Arithmetic, Grenoble, France, pp. 43-50,1991.
7. R. Z Zimmermann and W. Fichtner, "Low-power logic styles: CMOS versus pass-transistor logic," IEEE Journal for SolidState Circuits, vol.32, pp.1079-1090, July 1997.