Evaluation of blue gene/Q hardware support for transactional memories

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

Volumn , Issue , 2012, Pages 127-136

  Wang, Amy ^a   Gaudet, Matthew ^b   Wu, Peng ^c   Amaral, José Nelson ^b   Ohmacht, Martin ^c   Barton, Christopher ^a   Silvera, Raul ^a   Michael, Maged ^c  

^a IBM TORONTO LAB   (Canada)

^b UNIVERSITY OF ALBERTA   (Canada)

^c IBM RESEARCH   (United States)

Author keywords

Hardware transactionalmemories; Programmingmodel; Run time system; Software support

Indexed keywords

BEST-EFFORT; BLUE GENE; COARSE-GRAINED; END-TO-END SYSTEMS; HARDWARE SUPPORTS; PROGRAMMING MODELS; PROGRAMMINGMODEL; RUNTIMES; SEQUENTIAL EXECUTION; SOFTWARE STACKS; SOFTWARE SUPPORT; TIME SYSTEMS; TRANSACTIONAL MEMORY;

PARALLEL ARCHITECTURES; STORAGE ALLOCATION (COMPUTER);

HARDWARE;

EID: 84867556043     PISSN: 1089795X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2370816.2370836     Document Type: Conference Paper

References (21)

1. J. Bobba, K. Moore, H. Volos, L. Yen, M. D. Hill, M. M. Swift, and D. A. Wood. Performance pathologies in hardware transactional memory. In International Conference on Computer Architecture (ISCA), pages 81-91, San Diego, CA, USA, 2007.
2. C. C. S. Ananian, K. Asanovic, B. Kuszmaul, C. Leiserson, and S. Lie. Unbounded transactional memory. In High-Performance Computer Architecture (HPCA), pages 316-327, San Francisco, CA, USA, February 2005.
3. C. Cascaval, C. Blundell, M. Michael, H. W. Cain, P. Wu, S. Chiras, and S. Chatterjee. Software transactional memory: Why is it only a research toy? Communications of the Association for Computing Machinery, 51(11):40-46, November 2008.
4. J. Chung, L. Yen, S. Diestelhorst, M. Pohlack, M. Hohmuth, D. Christie, and D. Grossman. ASF: AMD64 extension for lock-free data structures and transactional memory. In Intern. Symposium on Microarchitecture (MICRO), pages 39-50, Atlanta, GA, USA, December 2010.
5. C. Click. Azul's experiences with hardware transactional memory. In HP Labs' Bay Area Workshop on Transactional Memory, 2009.
6. S. C. R. Cypher, M. Ekman, M. Karlsson, A. Landin, S. Yip, H. Zeffer, and M. Tremblay. Simultaneous speculative threading: a novel pipeline architecture implemented in sun's rock processor. In International Conference on Computer Architecture (ISCA), pages 484-495, Austin, TX, USA, 2009.
7. L. Dalessandro, M. F. Spear, and M. L. Scott. NOrec: Streamlining STM by abolishing ownership records. In Principles and practice of parallel programming, pages 67-78, Bangalore, India, January 2010.
8. D. Dice, Y. Lev, M. Moir, and D. Nussbaum. Early experience with a commercial hardware transactional memory implementation. In Architectural Support for Programming Languages and Operating Systems (ASPLOS), pages 157-168, Washington, DC, USA, March 2009.
9. P. Felber, C. Fetzer, P. Marlier, and T. Riegel. Time-based software transactional memory. IEEE Transactions on Parallel and Distributed Systems, 21(12):1793-1807, December 2010.
10. P. Felber, C. Fetzer, and T. Riegel. Dynamic performance tuning of word-based software transactional memory. In Principles and practice of parallel programming, pages 237-246, Salt Lake City, UT, USA, February 2008.
11. T. M. S. D. Group. Draft specification of transactional language constructs for C++ (version 1.1), 2012.
12. R. Haring, M. Ohmacht, T. Fox, M. Gschwind, D. Satterfield, K. Sugavanam, P. Coteus, P. Heidelberger, M. Blumrich, R. Wisniewski, A. Gara, G.-T. Chiu, P. Boyle, N. Chist, and C. Kim. The ibm blue gene/q compute chip. IEEE Micro, 32(2):48-60, March-April 2012.
13. M. Herlihy and J. E. Moss. Transactional memory: Architectural support for lock-free data structures. In International Conference on Computer Architecture (ISCA), pages 289-300, San Diego, CA, USA, May 1993.
14. Intel Corporation. Intel Architecture Instruction Set Extensions Programming Reference, 319433-012 edition, February 2012.
15. D. Kanter. Analysis of Haswell's transactional memory. http://www.realworldtech.com/page.cfm?ArticleID=RWT021512050738&p=1, February 2012. Real World Technologies.
16. C. C. Minh, J. Chung, C.Kozyrakis, and K. Olukotun. STAMP: Stanford transactional applications for multi-processing. In International Symposium on Workload Characterization (IISWC), pages 35-46, Seattle, WA, USA, September 2008.
17. C. C. Minh, M. Trautmann, J. Chung, A. McDonald, N. Bronson, J. Casper, C. Kozyrakis, and K. Olukotun. An effective hybrid transactional memory system with strong isolation guarantees. In International Conference on Computer Architecture (ISCA), pages 69-80, San Diego, CA, USA, 2007.
18. B. Saha, A.-R. Adl-Tabatabai, R. L. Hudson, C. C. Minh, and B. Hertzberg. McRT-STM: A high performance software transactional memory system for a multi-core runtime. In Principles and practice of parallel programming, pages 187-197, New York, NY, USA, January 2006.
19. M. F. Spear, M. M. Michael, and C. von Praun. RingSTM: scalable transactions with a single atomic instruction. In ACM Symp. on Parallelism in Algorithms and Architectures (SPAA), pages 275-284, Munich, Germany, June 2008.
20. J. M. Stone, H. S. Stone, P. Heidelberger, and J. Turek. Multiple reservations and the Oklahoma update. IEEE Parallel & Distributed Technology (PDT), 1(4):58-71, November 193.
21. C. Wang, W.-Y. Chen, Y. Wu, B. Saha, and A.-R. Adl-Tabataba. Code generation and optimization for transactional memory constructs in an unmanaged language. In Code Generation and Optimization (CGO), pages 34-48, San Jose, CA, USA, March 2007.