Application-aware prefetch prioritization in on-chip networks

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

Volumn , Issue , 2012, Pages 441-442

  Nachiappan, Nachiappan Chidambaram ^a   Mishra, Asit K ^b   Kandemir, Mahmut ^a   Sivasubramaniam, Anand ^a   Mutlu, Onur ^c   Das, Chita R ^a  

^a PENNSYLVANIA STATE UNIVERSITY   (United States)

^b INTEL CORPORATION   (United States)

^c CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

Interconnect; Multicore; Prefetching

Indexed keywords

DATA-PREFETCHING; HIDING MEMORY LATENCY; INTERCONNECT; MULTI CORE; MULTI PROCESSOR SYSTEMS; MULTI-CORE SYSTEMS; NETWORK ON CHIP; ON-CHIP NETWORKS; PERFORMANCE IMPROVEMENTS; POTENTIAL UTILITY; PREFETCHES; PREFETCHING; PRIORITIZATION;

VLSI CIRCUITS;

PARALLEL ARCHITECTURES;

EID: 84867553128     PISSN: 1089795X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2370816.2370886     Document Type: Conference Paper

References (10)

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3. E. Ebrahimi et al. Coordinated control of multiple prefetchers in multi-core systems. In MICRO-42, 2009.
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