Experiences with the sparse matrix-vector multiplication on a many-core processor

Proceedings of the 2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2012

Volumn , Issue , 2012, Pages 7-15

  Pichel, Juan C ^a   Rivera, Francisco F ^a  

^a Universidade de Santiago de Compostela ^*  (Spain)

Author keywords

many core; performance; power efficiency; sparse matrix

Indexed keywords

COMPLEX ARCHITECTURES; MANY-CORE; MULTI-CORE PROCESSOR; PERFORMANCE; POWER EFFICIENCY; SINGLE-CHIP; SPARSE MATRICES; SPARSE MATRIX-VECTOR MULTIPLICATION;

DISTRIBUTED PARAMETER NETWORKS; PROGRAM PROCESSORS;

PARALLEL PROCESSING SYSTEMS;

EID: 84867432441     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPDPSW.2012.17     Document Type: Conference Paper

References (13)

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