Analyzing the execution of sparse matrix-vector product on the Finisterrae SMP-NUMA system

Journal of Supercomputing

Volumn 58, Issue 2, 2011, Pages 195-205

  Pichel, Juan C ^a   Lorenzo, Juan A ^b   Heras, Dora B ^b   Cabaleiro, Jose C ^b   Pena, Tomás F ^b  

^a Centro de Supercomputacion de Galicia   (Spain)

^b UNIVERSITY OF SANTIAGO DE COMPOSTELA   (Spain)

Author keywords

Memory hierarchy; NUMA; Sparse matrix; Thread affinity

Indexed keywords

ITS ARCHITECTURE; MATRIX-VECTOR PRODUCTS; MEMORY ACCESS PATTERNS; MEMORY HIERARCHY; NUMA; SIGNIFICANT IMPACTS; SPARSE MATRICES; THREAD AFFINITY;

SUPERCOMPUTERS;

COMPUTER ARCHITECTURE;

EID: 80054888287     PISSN: 09208542     EISSN: 15730484     Source Type: Journal    
DOI: 10.1007/s11227-010-0392-4     Document Type: Article

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