Investigation of main memory bandwidth on intel single-chip cloud computer

3rd Many-Core Applications Research Community Symposium, MARC 2011

Volumn , Issue , 2011, Pages 107-110

  Melot, Nicolas ^a   Avdic, Kenan ^a   Kessler, Christoph ^a   Keller, Jörg ^b  

^a LINKÖPING UNIVERSITY   (Sweden)

^b UNIVERSITY OF HAGEN   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

HIGH PERFORMANCE NETWORKS; LINUX- OPERATING SYSTEM; MAIN MEMORY; MEMORY ACCESS; MEMORY ACCESS PATTERNS; MEMORY BANDWIDTHS; MEMORY CONTROLLER; OFF-CHIP; OFF-CHIP MEMORIES; ON CHIPS; SINGLE-CHIP;

CLOUD COMPUTING;

EID: 84870486690     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. J. Howard, S. Dighe, S. Vangal, G. Ruhl, N. Borkar, S. Jain, V. Erraguntla, M. Konow, M. Riepen, M. Gries, G. Droege, T. Lund-Larsen, S. Steibl, S. Borkar, V. De, and R. Van Der Wijngaart, "A 48-Core IA-32 messagepassing processor in 45nm CMOS using on-die message passing and DVFS for performance and power scaling," IEEE J. of Solid-State Circuits, vol. 46, no. 1, pp. 173-183, Jan. 2011.
2. R. Hultén, J. Keller, and C. Kessler, "Optimized on-chip-pipelined mergesort on the Cell/B.E." in Proceedings of Euro-Par 2010, vol. 6272, 2010, pp. 187-198.
3. K. Avdic, N. Melot, J. Keller, and C. Kessler, "Parallel sorting on Intel Single-Chip Cloud Computer," in Proc. A4MMC workshop on applications for multi- and many-core processors at ISCA-2011, 2011.