Evaluating dynamic partial reconfiguration in the integer pipeline of a FPGA-based opensource processor

Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL

Volumn , Issue , 2008, Pages 547-550

  Zaidi, Izhar ^a   Nabina, Atukem ^a   Canagarajah, C N ^a   Nunez Yanez, Jose ^a  

^a UNIVERSITY OF BRISTOL   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

CLOSED LOOP CONTROL SYSTEMS; COMPUTER CIRCUITS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); OPEN SYSTEMS; PIPELINES; RECONFIGURABLE HARDWARE;

DYNAMIC PARTIAL RECONFIGURATION; HARDWARE OPERATOR; OPEN SOURCES; OPEN-SOURCE; PARTIAL RECONFIGURATION; SILICON AREA; SPECIFIC ENERGY; TIGHTLY-COUPLED;

PIPELINE PROCESSING SYSTEMS;

EID: 54949088306     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2008.4630005     Document Type: Conference Paper

References (11)

1. Michael Ullmann, Michael Hubner, Bjorn Grimm, Jurgen Becker. "An FPGA Run-Time System for Dynamical On-Demand Reconfiguration." 0-7695-2132-0/04 (IPDPS'04) IEEE.
2. Francisco Barat, Murali Jayapala, Tom Vander Aa, Rudy Lauwereins, Geert Deconinck, and Henk Corporaal "Low Power Coarse-Grained Reconfigurable Instruction Set Processor" FPL 2003, LNCS 2778, pp. 230-239, 2003. Springer-Verlag Berlin Heidelberg 2003
3. Jurgen Becker, Michael Huebner, Michael Ullmann "Power Estimation and Power Measurement of Xilinx Virtex FPGAs: Trade-offs and Limitations." 07695-2009-/03 (SBCCI'03) IEEE
4. Mohammad Hosseinabady and Jose Nunez-Yanez "Fault-Tolerant Dynamically Reconfigurable NoC-based SoC." (To be published ASAP'08)
5. Gaisler Research LEON3 processor description.
6. GRLIB IP Library User's Manual Version 1.0.14 Jiri Gaisler, Sandi Habnic, Edvin Catovic, Gaisler Research, 2006.
7. Plan Ahead as Platform for partial Reconfiguration http://www.xilinx.com/ publications/xcellonline/xcell_55/xc_pdf/xc_prmethod55.pdf
8. Xilinx "Virtex-4 Configuration Guide, ug071" January 12, 2007.
9. Xiaofeng Wu and Tanya Vladimirova "A Self-reconfigurable System-on-Chip Architecture for Satellite On-Board Computer Maintenance" c. Jesshope and C. Egan (Eds.): ACSAC 2006, LNCS 4186, pp. 552 - 558, 2006. Springer-Verlag Berlin Heidelberg 2006.
10. K. Paulsson, M. Hubner, G. Auer, M. Dreschmann, L. Chen, J. Becker "Implementation of a Virtual Internal Configuration Access Port (JCAP) for Enabling Partial Self-Reconfiguration on Xilinx Spartan III FPGA's" 10.1109/FPL.2007.4380671.
11. Mateusz Majer "An FPGA based Dynamically Reconfigurable Platform: From Concept to Realization" 10.1109/FPL.2006.311364 [12] Jose Luis Nunez-Yanez, Vassilios Chouliaras. Jiri Gaisler "Dynamic Voltage Scaling in a FPGA-Based System-On-Chip" 10.1109/FPL.2007.4380689.