Via last technology for direct stacking of processor and flash

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2012, Pages 1327-1332

  Puschmann, René ^a   Böttcher, Mathias ^a   Ziesmann, Michael ^b   Bartusseck, Irene ^a   Windrich, Frank ^a   Fiedler, Conny ^a   John, Peggy ^a   Manier, Charles ^a   Zoschke, Kai ^a   Grafe, Jürgen ^a   Oppermann, Hermann ^a   Wolf, M Jürgen ^a   Lang, K Dieter ^a  

^a FRAUNHOFER IZM   (Germany)

^b NXP SEMICONDUCTORS   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP INTERCONNECTS; COPPER DEPOSITION; FLASH CHIPS; INTEGRATION SCHEME; MOBILE APPLICATIONS; NON-VOLATILE MEMORIES; PROCESSOR CHIPS; REDISTRIBUTION LAYERS; SPATIAL DIMENSION; THROUGH-SILICON-VIA;

DATA STORAGE EQUIPMENT; ELECTROCHEMICAL SENSORS; FLASH MEMORY;

TECHNOLOGY;

EID: 84866879011     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2012.6249006     Document Type: Conference Paper

References (6)

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3. Jansen, H. et al., "The black silicon method. VI. High aspect ratio trench etching for MEMS applications", Proc. Micro Electro Mechanical Systems, 1996, pp. 250-257
4. Jansen, H. et al., "The black silicon method. IV. The fabrication of three-dimensional structures in silicon with high apect ratios for scanning probe microscopy and other applications", Proc. Micro Electro Mechanical Systems, 1995
5. Puech, M. et al., "Fabrication of 3D packaging TSV using DRIE", Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS, 2008, pp. 109-114
6. Mercha, A. et al., "Comprehensive analysis of the impact of single and arrays of through silicon vias induced stress on high-k / metal gate CMOS performance", Electron Devices Meeting (IEDM), 2010, pp. 2.2.1-2.2.4