Enhanced barrier seed metallization for integration of high-density high aspect-ratio copper-filled 3D through-silicon via interconnects

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2012, Pages 822-826

  Civale, Yann ^a   Armini, Silvia ^a   Philipsen, Harold ^a   Redolfi, Augusto ^a   Velenis, Dimitrios ^a   Croes, Kristof ^a   Heylen, Nancy ^a   El Mekki, Zaid ^a   Vandersmissen, Kevin ^a   Beyer, Gerald ^a   Swinnen, Bart ^a   Beyne, Eric ^a  

^a IMEC   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

3D INTERCONNECT; BUILDING BLOCKES; ELECTRONICS DEVICES; HIGH ASPECT RATIO; HIGH DENSITY INTERCONNECTS; OPERATION SPEED; PROCESS INTEGRATION; SEED LAYER; THIN FILMS DEPOSITION; VOLUME SHRINKAGE;

DEPOSITION; ELECTRONICS PACKAGING; METALLIZING; THREE DIMENSIONAL COMPUTER GRAPHICS;

ASPECT RATIO;

EID: 84866876877     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2012.6248928     Document Type: Conference Paper

References (7)

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4. A. Redolfi, et al., "Integration of TSVs, wafer thinning and backside passivation on full 300mm CMOS wafers for 3D applications," in Proceedings of IEEE Electronic Components and Technology Conference, pp. 1122-1125, 2011.
5. L. Zhao, et al., "A new perspective of barrier material evaluation and process optimization," in Proceedings of IEEE International Interconnect Technology Conference, pp. 206-208, 1-3 June 2009.
6. Y. Civale, et al., "Thermal stability of copper Through-Silicon Via barriers during IC processing," in in Proceedings of IEEE International Interconnect Technology Conference, pp. 1-3, 2012
7. S. Armini, "Void-free filling of HAR TSVs using a wet alkaline Cu seed on CVD Co as a replacement for PVD Cu seed," Journal of the Electrochemical Society, 158, 2, H160-H165, 2011.