A novel scallop free TSV etching method in magnetic neutral loop discharge plasma

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2012, Pages 794-795

  Morikawa, Yasuhiro ^a   Murayama, Takahide ^a   Sakuishi, Toshiyuki ^a   Yoshii, Manabu ^a   Suu, Koukou ^a  

^a ULVAC INC   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DISCHARGE PLASMA; ETCHING METHOD; HIGH-SPEED OPERATION; LOW-POWER CONSUMPTION; PACKAGING DENSITY; PARALLEL PROCESSING; THROUGH-SILICON-VIA; WIRE LENGTH;

THREE DIMENSIONAL COMPUTER GRAPHICS;

TECHNOLOGY;

EID: 84866870755     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2012.6248923     Document Type: Conference Paper

References (6)

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3. Y. Morikawa, et al,. J. Vac. Sci. Technol. A19 (2000) 1747.
4. J. C. Lin et al., "High Density 3D Integration using CMOSFoundry Technologies for 28 nm node and beyond." IEEE IEDM 2010, 2.1.1
5. T. Nakamura et al., "Comparative Study of Side-Wall Roughness Effects on Leakage Currents in Through-Silicon Via Interconnects" IEEE 3D IC 2011, 2-4.
6. K. W. Lee et al., "High Reliable and Fine Size of 5-um Diameter Backside Cu Through-Silicon Via (TSV) for High Reliability and High-End 3-D LSIs" IEEE 3D IC 2011, 9-7.