PDN impedance and noise simulation of 3D SiP with a widebus structure

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2012, Pages 673-677

  Takatani, Hiroki ^a   Tanaka, Yosuke ^a   Oizono, Yoshiaki ^a   Nabeshima, Yoshitaka ^a   Okumura, Takafumi ^a   Sudo, Toshio ^a   Sakai, Atsushi ^b   Uchiyama, Shiro ^b   Ikeda, Hiroaki ^b  

^a SHIBAURA INSTITUTE OF TECHNOLOGY   (Japan)

^b ASSOCIATION OF SUPER ADVANCED ELECTRONICS TECHNOLOGIES ASET   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ANTI-RESONANCE; CONVENTIONAL MEMORIES; LOGIC CHIPS; MEMORY CHIPS; NOISE SIMULATION; ORGANIC SUBSTRATE; POWER SUPPLY; POWER-SUPPLY NOISE; SPICE MODEL; SYSTEM-IN-PACKAGE; THROUGH SILICON VIAS;

INTERNET PROTOCOLS; SUBSTRATES;

THREE DIMENSIONAL COMPUTER GRAPHICS;

EID: 84866868919     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2012.6248904     Document Type: Conference Paper

References (8)

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5. Jun So Pak et al, "Sharing Power Distribution Networks for enhanced Power Integrity by using Through-Silicon-Via," Proc. IEEE EDAPS, 2008.
6. Jun So Pak et al, "PDN Impedance Modeling and Analysis of 3D TSV IC by Using Proposed P/G TSV Array Model Based on Separated P/G TSV and Chip PDN Models," IEEE Trans. on CPMT, 2011, vol.1, no.2, pp.208-219
7. Nauman H. Khan et al, "Power Delivery Design for 3-D ICs Using Different Through-Silicon Via (TSV) Technologies," IEEE Trans. on VLSI Systems, 2011, vol.19, no.4, pp.647-658l.
8. Namhoon Kim et al, "Interposer Design Optimization for High Frequency Signal Transmission in Passive and Active Interposer using Through Silicon Via (TSV)," Proc. 61th ECTC, 2011, pp.1160-1167.