Sharing power distribution networks for enhanced power integrity by using through-silicon-via

2008 Electrical Design of Advanced Packaging and Systems Symposium, IEEE EDAPS 2008 - Proceedings

Volumn , Issue , 2008, Pages 9-12

  Pak, Jim So ^a   Kim, Jaemin ^a   Lee, Junho ^b   Lee, Hyungdong ^b   Park, Kunwoo ^b   Kim, Joungho ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

^b Hynix Semiconductor Inc   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

HIGH-FREQUENCY APPLICATIONS; INTERCONNECTION METHODS; POWER DISTRIBUTION NETWORKS; POWER INTEGRITIES; SHUNT CAPACITANCES; SILICON SUBSTRATES; THROUGH-SILICON-VIA; WIRE BONDINGS;

DISTRIBUTED PARAMETER NETWORKS; DISTRIBUTION OF GOODS; ELECTRIC NETWORK ANALYSIS; ELECTRIC POWER DISTRIBUTION; INDUCTANCE; PACKAGING; SILICON COMPOUNDS;

CHIP SCALE PACKAGES;

EID: 60649087374     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EDAPS.2008.4735985     Document Type: Conference Paper

References (8)

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4. C. Ryu, J. Lee, H. Lee, K, Lee, T. Oh, J, Kim, " High Frequency Electrical Model of Through Wafer Via for 3-D Stacked Chip Packaging," Electronics System-integration Technology Conf., Sept. 2006, vol 1, pp. 215-220.
5. C. Ryu, D. Chung, Junho Lee, K. Lee, T. Oh, J. Kim, "High frequency electrical circuit model of chip-to-chip vertical via interconnection for 3-D chip stacking package", IEEE 14th Topical Meeting on Electrical Performance of Electronic Packaging, pp. 151-154, Oct. 2005.
6. C. Ryu, J. Lee, H. Lee, K. Lee, T. Oh, J. Kim, " High Frequency Electrical Model of Through Wafer Via for 3-D Stacked Chip Packaging", Electronics System-integration Technology Conf, vol 1, pp. 215-220, Sept. 2006.
7. Jun So Pak, Chunghyun Ryu and Joungho Kim, "Electrical Characterization of Through Silicon Via (TSV) depending on Structural and Material Parameters based on 3D Full Wave Simulation," in Proceedings of the 9th international symposium on Electronic Materials and Packaging, Daejeon, Korea, November 21, 2007.
8. Jun So Pak, Chunghyun Ryu, Jaemin Kim, Yujeong Shim, Gawon Kim, and Joungho Kim, "Wideband Low Power Distribution Network Impedance of High Chip Density Package using 3-D Stacked Through Silicon Vias," in Proceedings of the Asia-Pacific Symposium on Electromagnetic Compatibility, Singapore, May 19-22, 2008, pp. 355-358.