Differential heating/cooling chip joining method to prevent chip package interaction issue in large die with ultra low-k technology

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2012, Pages 430-435

  Sakuma, Katsuyuki ^a   Smith, Kurt ^a   Tunga, Krishna ^a   Perfecto, Eric ^a   Wassick, Thomas ^a   Pompeo, Frank ^a   Nah, Jae Woong ^b  

^a IBM MICROELECTRONICS   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BASE PLATES; BONDING PROCESS; C-MODE SCANNING ACOUSTIC MICROSCOPE; CHIP INTERCONNECTS; CHIP-PACKAGE INTERACTION; DEVICE INTEGRATION; DIE PACKAGES; DIFFERENTIAL HEATING; ELEVATED TEMPERATURE; FLIP CHIP ASSEMBLIES; FLIP-CHIP PACKAGING; JOIN METHOD; JOINING METHOD; JOINING PROCESS; MODELING STUDIES; NON DESTRUCTIVE; NON-CONTACT; ORGANIC SUBSTRATE; PB-FREE; REFLECTOMETRY; REFLOW PROCESS; SI CHIPS; SILICON CHIP; SOLDER BRIDGING; SOLDER BUMP; STRESS-INDUCED; SUBSTRATE TEMPERATURE; TEMPERATURE DIFFERENCES; ULK LAYERS; ULTRA LOW-K; WARPAGES; WHITE LIGHT; X-RAY IMAGE;

CHIP SCALE PACKAGES; DIELECTRIC MATERIALS; FRACTURE; JOINING; LEAD; SCANNING ELECTRON MICROSCOPY; SILICON; SOLDERING; TECHNOLOGY; THERMAL EXPANSION;

SUBSTRATES;

EID: 84866858041     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2012.6248866     Document Type: Conference Paper

References (11)

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