Chip-package-interaction modeling of ultra low-k/copper back end of line

Proceedings of the IEEE 2007 International Interconnect Technology Conference - Digest of Technical Papers

Volumn , Issue , 2007, Pages 13-15

  Liu, X H ^a   Shaw, T M ^a   Lane, M W ^a   Liniger, E G ^a   Herbst, B W ^a   Questad, D L ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DELAMINATION; FINITE ELEMENT METHOD; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; STRESS ANALYSIS; THIN FILMS;

BACK END OF LINES (BEOL); CHIP PACKAGE INTERACTION (CPI); CHIP PACKAGE INTERACTION MODELING; ULK BEOL DELAMINATION;

DIELECTRIC DEVICES;

EID: 34748823731     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iitc.2007.382334     Document Type: Conference Paper

References (5)

1. D. C. Edelstein et al. "Comprehensive Reliability Evaluation of a 90 nm CMOS Technology with Cu/PECVD Low-K BEOL", International Reliability Physics Symposium, Phoenix, AZ, 2004, pp. 316-319
2. S. Sankaran et al. "A 45 nm CMOS node Cu/Low-k/Ultra Low-k PECVD SiCOH (k=2.4) BEOL Technology", IEDM Dec. 11-13, 2006
3. J. W. Hutchinson, Z. Suo, "Mixed mode cracking in layered materials", Advances in Applied Mechanics, Vol. 29, 1992, pp. 63-191.
4. X. H. Liu, M. W. Lane, T. M. Shaw, E. Simonyi, "Delamination in Patterned Films", to appear in International Journal of Solids and Structures, 2007
5. T. M. Shaw, E. Liniger, G. Bonilla, J.P. Doyle, B. Herbst, X. H. Liu and M. W. Lane, "Experimental Determination of the Toughness of Crack Stop Structures", IITC 2007