Two-phase flow boiling in a single layer of future high-performance 3D stacked computer chips

InterSociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, ITHERM

Volumn , Issue , 2012, Pages 597-605

  Szczukiewicz, Sylwia ^a   Borhani, Navid ^a   Thome, John Richard ^a  

^a EPFL   (Switzerland)

Author keywords

chip; cooling; evaporator; high speed; infra red; multi microchannels; refrigerant; silicon; two phase; visualization

Indexed keywords

ACTIVE COMPONENTS; BACK FLOW; BOILING PROCESS; CHIP; CMOS CHIPS; COMPUTER CHIPS; CROSS-SECTION AREA; EXPERIMENTAL CAMPAIGN; EXPERIMENTAL INVESTIGATIONS; FLOW DISTRIBUTION; FLOW INSTABILITIES; HEATED AREA; HIGH-SPEED; HIGH-SPEED FLOW VISUALIZATION; MICRO EVAPORATORS; MICRO-HEATERS; MICROORIFICES; MULTI-MICROCHANNELS; PARALLEL CHANNEL; R1234ZE; SINGLE LAYER; TEST SECTIONS; THERMAL PERFORMANCE; TWO-PHASE; TWO-PHASE FLOW BOILING; WORKING FLUID;

COOLING; ELECTRONICS ENGINEERING; EVAPORATORS; FLOW VISUALIZATION; MICROCHANNELS; ORIFICES; PHASE TRANSITIONS; REFRIGERANTS; SILICON; THREE DIMENSIONAL; VAPORS;

TWO PHASE FLOW;

EID: 84866172968     PISSN: 19363958     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ITHERM.2012.6231483     Document Type: Conference Paper

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