Sparse matrix-vector multiplication on a reconfigurable supercomputer with application

ACM Transactions on Reconfigurable Technology and Systems

Volumn 3, Issue 1, 2010, Pages

  Dubois, David ^a   Dubois, Andrew ^a   Boorman, Thomas ^a   Connor, Carolyn ^a   Poole, Steve ^b  

^a LOS ALAMOS NATIONAL LABORATORY   (United States)

^b OAK RIDGE NATIONAL LABORATORY   (United States)

Author keywords

Accelerator; Architecture; Conjugate gradient; FPGA; Hybrid computing; Iterative methods; Reconfigurable; Reconfigurable hardware; Sparse matrix vector multiplication

Indexed keywords

AVAILABLE BANDWIDTH; COMPUTATIONAL KERNELS; CONJUGATE GRADIENT; CONJUGATE GRADIENT ALGORITHMS; CUSTOMIZABLE; DATA LOCALITY; DOUBLE PRECISION; FLOATING POINTS; GENERAL PURPOSE PROCESSORS; HIGH MEMORY BANDWIDTH; HYBRID COMPUTING; ITERATIVE SOLVERS; MEMORY BANDWIDTHS; PEAK PERFORMANCE; POOR PERFORMANCE; PROCESSING ELEMENTS; RECONFIGURABLE; RECONFIGURABLE SUPERCOMPUTERS; SPARSE MATRICES; SPARSE MATRIX-VECTOR MULTIPLICATION; SUB-SYSTEMS; SUSTAINED PERFORMANCE; TIGHT COUPLING;

ARCHITECTURE; BANDWIDTH; CONJUGATE GRADIENT METHOD; DIGITAL ARITHMETIC; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); ITERATIVE METHODS; MATRIX ALGEBRA; MULTIPROCESSING SYSTEMS; PARTICLE ACCELERATORS; RECONFIGURABLE ARCHITECTURES; SUPERCOMPUTERS;

RECONFIGURABLE HARDWARE;

EID: 84864921475     PISSN: 19367406     EISSN: 19367414     Source Type: Journal    
DOI: 10.1145/1661438.1661440     Document Type: Article

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