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Volumn , Issue , 2008, Pages 239-247
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Sparse matrix-vector multiplication on a reconfigurable supercomputer
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Author keywords
FPGA; Iterative methods; Reconfigurable hardware; Sparse Matrix Vector Multiplication
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Indexed keywords
COMPUTATIONAL KERNELS;
CUSTOMIZABLE;
DATA LOCALITIES;
DOUBLE PRECISION;
FPGA;
GENERAL-PURPOSE PROCESSORS;
HIGH MEMORY BANDWIDTHS;
ITERATIVE SOLVERS;
MEMORY SUBSYSTEMS;
POOR PERFORMANCE;
PROCESSING ELEMENTS;
PROGRAMMABLE GATES;
RECONFIGURABLE HARDWARE;
RECONFIGURABLE SUPERCOMPUTERS;
SPARSE MATRICES;
SPARSE MATRIX-VECTOR MULTIPLICATION;
SPARSE MATRIX-VECTOR MULTIPLICATIONS;
COMPUTERS;
FIELD PROGRAMMABLE GATE ARRAYS (FPGA);
MULTIPROCESSING SYSTEMS;
ONLINE SEARCHING;
SUPERCOMPUTERS;
VECTORS;
ITERATIVE METHODS;
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EID: 60349131295
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1109/FCCM.2008.53 Document Type: Conference Paper |
Times cited : (9)
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References (12)
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