Physical modeling and analysis on improved endurance behavior of P-type floating gate NAND flash memory

2012 4th IEEE International Memory Workshop, IMW 2012

Volumn , Issue , 2012, Pages

  Lee, ChangHyun ^a   Fayrushin, Albert ^a   Hur, Sunghoi ^a   Park, Youngwoo ^a   Choi, Jungdal ^a   Choi, Jeonghyuk ^a   Chung, Chilhee ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

Endurance; Hole trapping; NAND flash memory; P type floating gate

Indexed keywords

COMPENSATION EFFECTS; CYCLING STRESS; DATA RETENTION; DEVICE SIMULATIONS; ERASE OPERATION; FLOATING GATES; HOLE CURRENT; HOLE TRAPPING; NAND FLASH; NAND FLASH MEMORY; P-TYPE; PHYSICAL MODEL; PHYSICAL MODELING; SI SUBSTRATES; TUNNEL OXIDES;

CELLS; COMPUTER SIMULATION; CYTOLOGY; MODELS; NAND CIRCUITS;

DURABILITY;

EID: 84864130442     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IMW.2012.6213655     Document Type: Conference Paper

References (4)

1. C. Shen, J. Pu, M. F. Li and B. J. Cho, "P-type floating gate for retention and P/E window improvement of flash memory devices", IEEE Trans. Electron Devices, vol. 54, no 8, pp.1910-1917.
2. W. Metzger, "How lifetime fluctuations, grain-boundary recombination, and junctions affect lifetime measurements and their correlation to silicon solar cell performance", Sol. Energy Mater. Sol. Cells 92 (2008) 1123.
3. G. Van den Bosch, G. Breuil, L. Cacciato, A. Rothschild, A. Jurczak, and J. Van Houdt, "Investigation of Window Instability in Program/Erase Cycling of TANOS NAND Flash Memory", Tech. Dig. of International Memory Workshop, 2009, pp. 84-87.
4. A. Fayrushin, C. Lee, Y. Park, J. Choi, J. Choi and C. Jung, "Endurance Prediction of Scaled NAND Flash Memory Based on Spatial Mapping of Erase Tunneling Current", Tech. Dig. of International Memory Workshop, 2011, pp. 87-90.