Endurance prediction of scaled NAND flash memory based on spatial mapping of erase tunneling current

2011 3rd IEEE International Memory Workshop, IMW 2011

Volumn , Issue , 2011, Pages

  Fayrushin, Albert ^a   Lee, Changhyun ^a   Park, Youngwoo ^a   Choi, Jungdal ^a   Choi, Jeonghyuk ^a   Chung, Chilhee ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

endurance; Flash; modeling; NAND; reliability

Indexed keywords

ABSOLUTE VALUES; FLASH; MIDGAP VOLTAGE; NAND; NAND FLASH MEMORY; PREDICTION TECHNIQUES; PROGRAM/ERASE; REFERENCE DEVICES; SIZE AND SHAPE; SPATIAL MAPPING; SPECIFIC DISTRIBUTION; TRAPPED CHARGE; TUNNEL OXIDES; TUNNELING CURRENT;

DISTRIBUTION FUNCTIONS; DURABILITY; ELECTRIC CHARGE; ELECTRON TUNNELING; NAND CIRCUITS;

FLASH MEMORY;

EID: 79959984937     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IMW.2011.5873215     Document Type: Article

References (4)

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2. S. Wolf, Silicon Processing for the VLSI Era. vol.4. Deep-submicron Process Technology. Sunset Beach, Ca:Lattice Press, 2002, pp.94-95.
3. A. Fayrushin, K.S. Seol, J.H. Na, S.H. Hur, J. Choi, K. Kim, "The new program/erase degradation mechanism of NAND flash memory devices," Electron Devices Meeting (IEDM), 2009 IEEE International, Session 34, 7-9 Dec. 2009.
4. C.H. Lee et al., "A highly manufacturable integration technology for 27 nm 2 and 3bit/cell NAND FLASH memory", Electron Devices Meeting (IEDM), 2010 IEEE International, Session 5, 6-8 Dec. 2010.